Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1839
16.8.19
Software Reset Register (SW_RST)—Offset 2Fh
Access Method
Default: 00h
Bit
Range
Default &
Access
Field Name (ID): Description
7:4
0h
RO
Rsvd (reserved):
Reserved.
3:0
0h
RW
Data Timeout Counter Value (data_timeout_cnt_val):
This value determines the
interval by which DAT line timeouts are detected. For more information about timeout
generation, refer to the Data Timeout Error in the Error Interrupt Status register.
Timeout clock frequency will be generated by dividing the base clock TMCLK value by
this value. When setting this register, prevent inadvertent timeout events by clearing
the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register).
•
•
1111b Reserved
•
1110b = TMCLK x 2^27
•
.... ....
•
0001b = TMCLK x 2^14
•
0000b = TMCLK x 2^13
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
rs
vd
sw_rst
_dat_ln
sw_rs
t_cmd_ln
sw_rst_all
Bit
Range
Default &
Access
Field Name (ID): Description
7:3
0h
RO
Reserved (rsvd):
Reserved.