Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
1842
Datasheet
8
0b
RO
Card Interrupt (crd_int): 
Writing this bit to 1 does not clear this bit. It is cleared by 
resetting the SD card interrupt factor. In 1-bit mode, the Host Controller shall detect the 
Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt 
signal is sampled during the interrupt cycle, so there are some sample delays between 
the interrupt signal from the SD card and the interrupt to the Host System. When this 
status has been set and the Host Driver needs to start this interrupt service, Card 
Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 
in order to clear the card interrupt statuses latched in the Host Controller and to stop 
driving the interrupt signal to the Host System. After completion of the card interrupt 
service (It should reset interrupt factors in the SD card and the interrupt signal may not 
be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt 
signal again. Interrupt detected by DAT[1] is supported when there is a card per slot. In 
case of shared bus, interrupt pins are used to detect interrupts. If 000b is set to 
Interrupt Pin Select in the Shared Bus Control register, this status is effective. Non-zero 
value is set to Interrupt Pin Select, INT_A, INT_B or INT_C is then used to device 
interrupts. 
1 = Generate Card Interrupt 
0 = No Card Interrupt 
7
0b
RW/1C
Card Removal (crd_rm): 
This status is set if the Card Inserted in the Present State 
register changes from 1 to 0. When the Host Driver writes this bit to 1 to clear this 
status, the status of the Card Inserted in the Present State register should be 
confirmed. Because the card detect state may possibly be changed when the Host Driver 
clear this bit and interrupt event may not be generated. 
1  =  Card  removed 
0 = Card state stable or Debouncing 
6
0b
RW/1C
Card Insertion (crd_ins): 
This status is set if the Card Inserted in the Present State 
register changes from 0 to 1. When the Host Driver writes this bit to 1 to clear this 
status, the status of the Card Inserted in the Present State register should be 
confirmed, because the card detect state may possibly be changed when the Host Driver 
clears this bit and interrupt event may not be generated. 
1 Card inserted 
0 Card state stable or Debouncing 
5
0b
RW/1C
Buffer Read Ready (buf_rd_rdy): 
This status is set if the Buffer Read Enable changes 
from 0 to 1. Refer to the Buffer Read Enable in the Present State register. While 
performing tuning procedure (Execute Tuning is set to 1), Buffer Read Ready is set to 1 
for every CMD19 execution. 
1 = Ready to read buffer 
0 = Not ready to read buffer 
4
0b
RW/1C
Buffer Write Ready (buf_wr_rdy): 
This status is set if the Buffer Write Enable 
changes from 0 to 1. Refer to the Buffer Write Enable in the Present State register. 
1 = Ready to write buffer 
0 = Not ready to write buffer 
3
0b
RW/1C
DMA Interrupt (dma_int): 
This status is set if the Host Controller detects the Host 
SDMA Buffer boundary during transfer. Refer to the Host SDMA Buffer Boundary in the 
Block Size register. Other DMA interrupt factors may be added in the future. In case of 
ADMA, by setting Int field in the descriptor table, Host Controller generates this 
interrupt. Suppose that it is used for debugging. This interrupt shall not be generated 
after the Transfer Complete. 
1 = DMA Interrupt is generated 
0 = No DMA Interrupt 
2
0b
RW/1C
Block Gap Event (blk_gap_event): 
If the Stop At Block Gap Request in the Block Gap 
Control register is set, this bit is set when both a read / write transaction is stopped at a 
block gap. If Stop At Block Gap Request is not set to 1, this bit is not set to 1. (1) In 
the case of a Read Transaction
 This bit is set at the falling edge of the DAT Line 
Active Status, when the transaction is stopped at SD Bus timing. The Read Wait shall be 
supported in order to use this function. Refer to Section 3.12.3 for timing details. p](1) 
In the case of a Write Transaction
 This bit is set at the falling edge of Write Transfer 
Active Status (after getting CRC status at SD Bus timing). Refer to Section 3.12.4 for 
more details on the sequence of events. 
1 = Transaction stopped at block gap 
0 = No Block Gap Event 
Bit 
Range
Default & 
Access
Field Name (ID): Description