Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1843
16.8.21
Error Interrupt Status Register (ERR_INT_STATUS)—Offset 32h
Signals defined in this register can be enabled by the Error Interrupt Status Enable
register, but not by the Error Interrupt Signal Enable register. The interrupt is
generated when the Error Interrupt Signal Enable is enabled and at least one of the
statuses is set to 1. Writing to 1 clears the bit, and writing to 0 keeps the bit
unchanged. More than one status can be cleared at the one register write.
Access Method
Default: 0000h
1
0b
RW/1C
Transfer Complete (tx_comp):
This bit is set when a read / write transfer and a
command with busy is completed. (1) In the case of a Read Transaction This bit is
set at the falling edge of Read Transfer Active Status. This interrupt is generated in two
cases. The first is when a data transfer is completed as specified by data length (After
the last data has been read to the Host System). The second is when data has stopped
at the block gap and completed the data transfer by setting the Stop At Block Gap
Request in the Block Gap Control register (After valid data has been read to the Host
System). Refer to Section 3.12.3 for more details on the sequence of events. (2) In the
case of a Write Transaction
This bit is set at the falling edge of the DAT Line Active
Status. This interrupt is generated in two cases. The first is when the last data is written
to the SD card as specified by data length and the busy signal released. The second is
when data transfers are stopped at the block gap by setting Stop At Block Gap Request
in the Block Gap Control register and data transfers completed. (After valid data is
written to the SD card and the busy signal released). Refer to Section 3.12.4 for more
details on the sequence of events. (3) In the case of a command with busy This bit
is set when busy is de-asserted. Refer to DAT Line Active and Command Inhibit (DAT) in
the Present State register. Refer to the spec for the relationship between Transfer
Complete and Data Timeout Error.
•
•
1 = Command execution is completed
•
0 = Not complete
While performing tuning procedure (Execute Tuning is set to 1), Transfer Complete is
not set to 1.
0
0b
RW/1C
Command Complete (cmd_comp):
This bit is set when get the end bit of the
command response. Auto CMD12 and Auto CMD23 consist of two responses. Command
Complete is not generated by the response of CMD12 or CMD23 but generated by the
response of a read/write command. Refer to Command Inhibit (CMD) in the Present
State register for how to control this bit. Command Timeout Error has higher priority
than Command Complete. If both bits are set to 1, it can be considered that the
response was not received correctly. For a tabular description of the relationship
between these two bits, refer to the description of Command Complete in the spec.
•
•
1 = Command complete
•
0 = No command complete
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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ceata_er
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rsvd
adma_er
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cmd12_e
rr
cur_limit_e
rr
data_end_bit_e
rr
data_crc
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data_time
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cmd_in
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cmd_e
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cmd_crc
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cm
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