Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1844
Datasheet
Bit
Range
Default &
Access
Field Name (ID): Description
15
0b
RW
Vendor Specific Error Status (vend_spec_err_status):
Reserved.
14
0b
RW
Boot Command Timeout Error (boot_cmd_timeout_err):
Occur if the boot are
access command is issued to the agent which has no permission to access the boot
area.
13
0b
RW
CEATA Error (ceata_err):
Occurs when ATA command termination has occured due to
an error condition the device has encountered.
12
0b
RW
Target Response Error (tgt_rsp_err):
Occurs when detecting ERROR in
m_hresp(dma transaction).
11:10
0h
RO
Reserved (rsvd):
Reserved.
9
0b
RW
ADMA Error (adma_err):
This bit is set when the Host Controller detects errors during
ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the
ADMA Error Status Register. In addition, the Host Controller generates this Interrupt
when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error
State
in the ADMA Error Status indicates that an error occurs in ST_FDS state.The Host
Driver may find that Valid bit is not set at the error descriptor.
•
•
0 = error
•
1 = no error
8
0b
RW
Auto CMD12 Error (cmd12_err):
Auto CMD12 and Auto CMD23 use this error status.
This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status
register has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only
when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to
the previous command error.
•
•
1 = error
•
0 = no error
7
0b
RW
Current Limit Error (cur_limit_err):
By setting the SD Bus Power bit in the Power
Control register, the Host Controller is requested to supply power for the SD Bus. If the
Host Controller supports the Current Limit function, it can be protected from an illegal
card by stopping power supply to the card in which case this bit indicates a failure
status. Reading 1 means the Host Controller is not supplying power to SD card due to
some failure. Reading 0 means that the Host Controller is supplying power and no error
has occurred. The Host Controller may require some sampling time to detect the current
limit. If the Host Controller does not support this function, this bit shall always be set to
0.
•
•
1 = power fail
•
0 = no error
6
0b
RW
Data End Bit Error (data_end_bit_err):
Occurs either when detecting 0 at the end
bit position of read data which uses the DAT line or at the end bit position of the CRC
Status.
•
•
1 = error
•
0 = no error
5
0b
RW
Data CRC Error (data_crc_err):
Occurs when detecting CRC error when transferring
read data which uses the DAT line or when detecting the Write CRC status having a
value of other than 010b.
4
0b
RW
Data Timeout Error (data_timeout_err):
This bit is set when detecting one of
following timeout conditions.
•
•
Busy timeout for R1b,R5b type
•
Busy timeout after Write CRC status
•
Write CRC Status timeout
•
Read Data timeout
•
1 = time out
•
0 = no error