Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1847
Default: 0000h
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rs
vd0
ce
ata_err_en
tgt_r
sp_err_en
rs
vd
tune_e
rr
_stat_en
adma_e
rr
_stat_en
cmd12_e
rr
_stat_en
cur_limit_e
rr
_stat_en
data_end_bit_e
rr
_stat_en
data_cr
c_e
rr
_stat_en
data_time
out_e
rr
_stat_en
cmd_in
d_er
r_stat_e
n
cmd_e
n
d_b
it_er
r_stat_e
n
cmd_cr
c_er
r_stat_e
n
cmd_time
ou
t_e
rr_stat_en
Bit
Range
Default &
Access
Field Name (ID): Description
15:14
0b
RO
Rsvd0 (rsvd0):
Reserved.
13
0b
RW
CEATA Error Enable (ceata_err_en):
0 = masked
12
0b
RW
Target Response Error Enable (tgt_rsp_err_en):
0 = masked
11
0b
RO
Rsvd (rsvd):
Reserved.
10
0b
RW
Tuning Error Status Enable (tune_err_stat_en):
•
•
1 = enabled
•
0 = masked
9
0b
RW
ADMA Error Status Enable (adma_err_stat_en):
•
•
1 = enabled
•
0 = masked
8
0b
RW
Auto CMD12 Error Status Enable (cmd12_err_stat_en):
•
•
1 = enabled
•
0 = masked
7
0b
RW
Current Limit Error Status Enable (cur_limit_err_stat_en):
•
•
1 = enabled
•
0 = masked
6
0b
RW
Data End Bit Error Status Enable (data_end_bit_err_stat_en):
•
•
1 = enabled
•
0 = masked
5
0b
RW
Data CRC Error Status Enable (data_crc_err_stat_en):
•
•
1 = enabled
•
0 = masked
4
0b
RW
Data Timeout Error Status Enable (data_timeout_err_stat_en):
•
•
1 = enabled
•
0 = masked