Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1851
16.8.26
Auto CMD12 Error Status Register and Host Control 2 Register 
(CMD12_ERR_STAT_HOST_CTRL_2)—Offset 3Ch
Access Method
Default: 00000000h
1
0b
RW
Command CRC Error Signal Enable (cmd_crc_err_stat_en): 
1  =  enabled 
0  =  masked 
0
0b
RW
Command Timeout Error Signal Enable (cmd_timeout_err_stat_en): 
1  =  enabled 
0  =  masked 
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
BAR Type: 
PCI Configuration Register (Size: 32 bits)
BAR Reference: 
[B:0, D:18, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pr
ese
t_v
alu
e
asyn
c_int
R
SVD0
sampl
ing_c
lock
exec
u
te_tu
nin
g
dr
iver
_s
tre
n
gth
vl
uhs_mod
e
rs
vd
cm
d_not_is
s_cmd12_err
rs
vd
1
cm
d12_
in
d_err
cm
d12_
en
d_b
it_er
r
cm
d1
2
_
cr
c_
er
r
cmd12_timeout_err
cmd12_no
t_e
xe
Bit 
Range
Default & 
Access
Field Name (ID): Description
31
0b
RW
Preset Value (preset_value): 
Host Controller Version 3.00 supports this bit. As the 
operating SDCLK frequency and I/O driver strength depend on the Host System 
implementation, it is difficult to determine these parameters in the Standard Host 
Driver. When Preset Value Enable is set to automatic This bit enables the functions 
defined in the Preset Value registers. 
1 = Automatic Selection by Preset Value are Enabled 
0 SDCLK and Driver Strength are controlled by Host Driver 
If this bit is set to 0, SDCLK Frequency Select, Clock Generator Select in the Clock 
Control register and Driver Strength Select in Host Control 2 register are set by Host 
Driver. If this bit is set to 1, SDCLK Frequency Select, Clock Generator Select in the 
Clock Control register and Driver Strength Select in Host Control 2 register are set by 
Host Controller as specified in the Preset Value registers.
30
0b
RW
Asynchronous Interrupt (async_int): 
This bit can be set to 1 if a card support 
asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the 
Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used 
in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control 
register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous 
interrupt period to save power. During this period, the Host Controller continues to 
deliver Card Interrupt to the host when it is asserted by the Card. Usage: It is 
recommended that Synchronous Interrupt mode be used for SDIO Controller by setting 
this be to '0'. If Asynchronous Interrupt Enable mode is used, it is required that this bit 
remain '0' until SD initialization sequence is complete. 
1 = Enabled 
0  =  Disabled