Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1855
16.8.31
Force Event Register for Error Interrupt Status
(FORCE_EVENT_ERR_INT_STAT)—Offset 52h
Error Interrupt Status register can be written. The effect of a write to this address will
be reflected in the Error Interrupt Status Register if the corresponding bit of the Error
Interrupt Status Enable Register is set.
• Writing 1 : set each bit of the Error Interrupt Status Register
• Writing 0 : no effect
• Writing 0 : no effect
Note: By setting this register, the Error Interrupt can be set in the Error Interrupt
Status register. In order to generate interrupt signal, both the Error Interrupt Status
Enable and Error Interrupt Signal Enable shall be set.
Access Method
Default: 0000h
4
0b
RW
Force Event for Auto CMD12 Index Error (cmd12_ind_err):
•
•
1 = Interrupt is generated
•
0 = No Interrupt
3
0b
RW
Force Event for Auto CMD12 End Bit Error (cmd12_end_bit_err):
•
•
1 = Interrupt is generated
•
0 = No Interrupt
2
0b
RW
Force Event for Auto CMD12 CRC Error (cmd12_crc_err):
•
•
1 = Interrupt is generated
•
0 = No Interrupt
1
0b
RW
Force Event for Auto CMD12 Timeout Error (cmd12_timeout_err):
•
•
1 = Interrupt is generated
•
0 = No Interrupt
0
0b
RW
Force Event for Auto CMD12 Not Executed (cmd12_not_exe):
•
•
1 = Interrupt is generated
•
0 = No Interrupt
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rs
vd
0
ce
ata_err
tgt_r
sp_err
rs
vd
ad
m
a_err
cmd
1
2
_
er
r
cur_li
m
it_e
rr
data_e
nd_bit_err
data_crc_err
data_ti
m
eout_err
cm
d_
in
d
_
er
r
cm
d_e
n
d_b
it_er
r
cm
d
_
crc_e
rr
cmd_ti
me
out_e
rr
Bit
Range
Default &
Access
Field Name (ID): Description
15:14
00b
RO
Reserved 0 (rsvd0):
Reserved.