Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1904
Datasheet
16.10.24 Normal Interrupt Signal Enable Register (NRM_INT_SIG_EN)—
Offset 38h
This register is used to select which interrupt status is indicated to the Host System as
the interrupt. These status bits all share the same 1 bit interrupt line. Setting any of
these bits to 1 enables interrupt generation.
Access Method
Default: 0000h
3
0b
RW
Command Index Error Status Enable (cmd_ind_err_stat_en):
•
•
1 = enabled
•
0 = masked
2
0b
RW
Command End Bit Error Status Enable (cmd_end_bit_err_stat_en):
•
•
1 = enabled
•
0 = masked
1
0b
RW
Command CRC Error Status Enable (cmd_crc_err_stat_en):
•
•
1 = enabled
•
0 = masked
0
0b
RW
Command Timeout Error Status Enable (cmd_timeout_err_stat_en):
•
•
1 = enabled
•
0 = masked
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:23, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
fix
ed_0
rsvd
b
oot_te
rm_int_si
g_en
boot_ac
k_rcv_si
g
_e
n
crd
_
int_si
g_en
cr
d_r
m
_si
g
_e
n
crd
_
ins_si
g_en
buf_rd_
rdy_si
g
_e
n
bu
f_wr
_r
dy_si
g
_en
dma_int_si
g_en
blk
_
g
ap_e
ven
t_s
ig
_
en
tx
_c
omp_si
g_en
cmd_
co
mp_si
g
_e
n
Bit
Range
Default &
Access
Field Name (ID): Description
15
0b
RO
Fixed to 0 (fixed_0):
The Host Driver shall control error interrupts using the Error
Interrupt Signal Enable register.
14:11
0h
RO
Reserved (rsvd):
Reserved.
10
0b
RW
Boot Terminate Interrupt Signal Enable (boot_term_int_sig_en):
0 = masked
9
0b
RW
Boot Acknowledge Receive Signal Enable (boot_ack_rcv_sig_en):
0 = masked