Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1916
Datasheet
22:20
0h
RW
Interrupt Pin Select (int_pin):
Interrupt pin inputs are enabled by this field. Enable
of unsupported interrupt pin is meaningless.
•
•
000b = Interrupt is detected by theInterrupt Cycle.
•
xx1b = INT_A is enabled
•
x1xb = INT_B is enabled
•
1xxb = INT_C is enabled
19
0b
RO
RSVD2:
Reserved
18:16
0h
RW
Clock Pin Select (clk_pin):
One of clock pin outputs is selected by this field. Selection
of unsupported clock pins is meaningless. Refer to Figure 2-38 for the timing of clock
outputs.
•
•
000b = Clock Pins are disabled
•
001b = CLK[1] is selected
•
010b = CLK[2] is selected
•
. . .
•
111b = CLK[7] is Selected
15
0b
RO
RSVD3:
Reserved
14:8
0h
RO
Bus Width Preset (bus_width):
Shared bus supports mixing of 4-bit and 8-bit bus
width devices. Each bit of this field specifies the bus width for each embedded device.
The number of devices supported is specified by Number of Clock Pins, and a maximum
of 7 devices are supported. This field is effective when multiple devices are connected to
a shared bus (Slot Type is set to 10b in the Capabilities register). In the other case,
Extended Data Transfer Width in the Host Control 1 register is used to select 8-bit bus
width. As use of 1-bit mode is not intended for shared bus, Data Transfer Width in the
Host Control 1 register should be set to 1.
•
•
D24 = Bus width preset for Device 1
•
D25 = Bus width preset for Device 2
•
D26 = Bus width preset for Device 3
•
D27 = Bus width preset for Device 4
•
D28 = Bus width preset for Device 5
•
D29 = Bus width preset for Device 6
•
D30 = Bus width preset for Device 7
The function of each bit is defined as follows:
•
•
0 = 4 bit buswidth mode
•
1 = 8 bit buswidth mode
7:6
0b
RO
RSVD4:
Reserved
5:4
0h
RO
Number of Interrupt Pins (num_int_pin):
This field indicates support of interrupt
input pins for shared bus system. Three asynchronous interrupt pins are defined,
INT_A#, INT_B# and INT_C#. Which interrupt pin is used is determined by the system.
Each one is driven by open drain and then wired OR connection is possible.
•
•
00b = Interrupt Input Pin is not supported
•
01b = INTA is Supported
•
10b = INTA and INTB are supported
•
11b = INTA, INTB and INTC are supported
3
0b
RO
RSVD5:
Reserved
2:0
0h
RO
Number of Clock Pins (num_clk_pin):
This field indicates support of clock pins to
select one of devices for shared bus system. Up to 7 clock pins can be supported.
Shared bus is supported by specific system. Then the Standard Host Driver does not
support control of these clock pins.
•
•
000b Shared bus is not supported
•
001b 1 SDCLK pin is supported
•
010b 2 SDCLK pins are supported
•
. . .
•
111b 7 SDCLK pins are supported
Bit
Range
Default &
Access
Field Name (ID): Description