Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1921

The SoC contains a set of registers that shadow the contents of the legacy IDE 
registers. The behavior of the Command and Control Block registers, PIO, and DMA 
data transfers, resets, and interrupts are all emulated.

The SoC will assert INTR when the master device completes the EDD command 
regardless of the command completion status of the slave device. If the master 
completes EDD first, an INTR is generated and BSY will remain '1' until the slave 
completes the command. If the slave completes EDD first, BSY will be '0' when the 
master completes the EDD command and asserts INTR. Software must wait for busy to 
clear (0) before completing an EDD command, as required by the ATA5 through ATA7 
(T13) industry standards.

The SATA host controller supports 48-bit LBA through the host-to-device register FIS 
when accesses are performed using writes to the task file. The SATA host controller will 
ensure that the correct data is put into the correct byte of the host-to-device FIS. 

Host & Link Initiated Power 
Management

Capability for the host controller or device to request Partial 
and Slumber interface power states

Staggered Spin-Up

Enables the host to spin up hard drives sequentially to prevent 
power load problems on boot

Command Completion 
Coalescing

Reduces interrupt and completion overhead by allowing a 
specified number of commands to complete and then 
generating an interrupt to process the commands

Native Command Queuing (NCQ)

N/A

Supported

Auto Activate for DMA

N/A

Supported

Hot Plug Support

N/A

Supported

Asynchronous Signal Recovery

N/A

Supported

3 Gb/s Transfer Rate

Supported

Supported

ATAPI Asynchronous Notification

N/A

Supported

Host & Link Initiated Power Management 

N/A

Supported

Staggered Spin-Up

Supported

Supported

Command Completion Coalescing

N/A

N/A