Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1926
Datasheet
17.5.3
Device Status (STS)—Offset 6h
Access Method
Default: 02B0h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
0
ID
FBE
SE
E
WCC
PE
E
VG
A
MW
IE
SC
E
BME
MSE
IOSE
Bit
Range
Default &
Access
Description
15:11
0b
RO
RSVD0:
Reserved
10
0h
RW
Interrupt Disable (ID):
This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation. When set, internal INTx# will not be generated. When cleared,
internal INTx# is generated if there is an interrupt and MSI is not enabled.
9
0h
RO
Fast Back-to-Back Enable (FBE):
Reserved.
8
0h
RW
SERR# Enable (SEE):
When set to 1, the HBA is allowed to generate SERR# on DPD or
SATAGC.URD event that is enabled for SERR# generation. When cleared to 0, it is not.
7
0h
RO
Wait Cycle Enable (WCC):
Reserved.
6
0h
RW
Parity Error Response Enable (PEE):
When set, the SATA Controller will corrupt the
outbound DATA FIS CRC if a forwarded data parity error is indicated.
5
0h
RO
VGA Palette Snooping Enable (VGA):
Reserved.
4
0h
RO
Memory Write and Invalidate Enable (MWIE):
Reserved.
3
0h
RO
Special Cycle Enable (SCE):
Reserved.
2
0h
RW
Bus Master Enable (BME):
Controls the SATA Controller's ability to act as a master for
data transfers. This bit does not impact the generation of completions for split
transaction commands.
1
0h
RW
Memory Space Enable (MSE):
Controls access to the SATA Controller's target
memory space (for AHCI).
0
0h
RW
I/O Space Enable (IOSE):
Controls access to the SATA Controller's target I/O space.
Type:
PCI Configuration Register
(Size: 16 bits)
15
12
8
4
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
DPE
SS
E
RMA
RT
A
ST
A
DE
V
T
DP
D
FBC
RSVD
0
RSV
CL
IS
RSVD
1