Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1927

Default: 00h

15

0h

RW/1C

Set when the SATA Controller detects a parity error on 

its interface.

14

0h

RW/1C

Set when SATA Controller generates an SERR#.

13

0h

RW/1C

Set when the SATA Controller receives a 

master abort to a cycle it generated.

12

0h

RW/1C

Set when the SATA Controller receives a target 

abort to a cycle it generated.

11

0h

RW/1C

This bit must be set by a target device 

whenever it terminates a transaction with Target-Abort. Devices that will never signal 

Target-Abort do not need to implement this bit.

10:9

1h

RO

Controls the device select time for the SATA 

Controller's PCI interface.

8

0h

RW/1C

Set when the SATA Controller, as a 

master, either detects a parity error or sees the parity error line asserted, and the parity 

error response bit (bit 6 of the command register) is set. This bit can only be set on read 

completions received from the backbone where there is a parity error.

7

1h

RO

Reserved.

6

0b

RO

Reserved

5

1h

RO

Reserved.

4

1h

RO

Indicates the presence of a capabilities list. The minimum 

requirement for the capabilities list must be PCI power management for the SATA 

Controller.

3

0h

RO

Reflects the state of INTx# messages, IRQ14 or IRQ15. This bit 

is set when the interrupt is to be asserted. This bit is a 0 after the interrupt is cleared

2:0

0b

RO

Reserved

PCI Configuration Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

0

RID

7:0

00h

RO

Indicates stepping of the host controller hardware.