Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1942
Datasheet
17.5.32
Message Signaled Interrupt Message Address (MA)—Offset 84h
Access Method
Default: 00000000h
17.5.33
Message Signaled Interrupt Message Data (MD)—Offset 88h
Access Method
Default: 0000h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
0
C64
MME
MMC
MSIE
Bit
Range
Default &
Access
Description
15:8
0b
RO
RSVD0:
Reserved
7
0h
RO
64 Bit Address Capable (C64):
Capable of generating a 32-bit message only.
6:4
0h
RO
Multiple Message Enable (MME):
When this field is cleared to 000 (and MSIE is set),
only a single MSI message will be generated for all SATA ports, and bits [15:0] of the
message vector will be driven from MD[15:0].
3:1
0h
RO
Multiple Message Capable (MMC):
Not supported.
0
0h
RW
MSI Enable (MSIE):
If set, MSI is enabled and traditional interrupt pins are not used
to generate interrupts. Note that CMD.ID bit has not effect on MSI. Software must clear
this bit to 0 to disable MSI first before changing the number of messages allocated in
the MMC field. Software must also make sure this bit is cleared to 0 when operating in
legacy mode (for AHCI SKUs when GHC.AE = 0). This bit is RW when CC.SCC is not 01h
and is read-only 0 when CC.SCC is 01h.
Type:
PCI Configuration Register
(Size: 32 bits)
MA:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDR
RSVD0
Bit
Range
Default &
Access
Description
31:2
0h
RW
Address (ADDR):
Lower 32 bits of the system specified message address, always
DWORD aligned.
1:0
0b
RO
RSVD0:
Reserved
Type:
PCI Configuration Register
(Size: 16 bits)
MD: