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Intel E3815 FH8065301567411 Data Sheet

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FH8065301567411
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Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1945
17.5.36
Test Mode Register (TM)—Offset 94h
Access Method
Default: 00000000h
17.5.37
SATA General Configuration (SATAGC)—Offset 9Ch
Access Method
Default: 00000000h
8
0h
RO
Port 0 Present (P0P): 
When set, the SATA controller has detected the presence of a 
device on port 0. It may change at any time. Clearing P0E bit leads to clearing of this bit 
after implementation delay. Note: For system software that intends to clear all PCS.PxE 
bits that are previously 1 to 0 and then to 1 again in two consecutive write cycles, 
software shall poll on this bit being 0 before setting P0E bit to 1.
7:2
0b
RO
RSVD1: 
Reserved
1
0h
RW
Port 1 Enabled (P1E): 
When MAP.SPD[1] is 1, this bit is reserved and read-only 0. 
Otherwise if none of the above is true, this bit is RW and same as P0E but for port 1 and 
takes precedence over P1CMD.SUD.
0
0h
RW
Port 0 Enabled (P0E): 
When MAP.SPD[0] is 1, this bit is reserved and read-only 0. 
When set, the port is enabled. When cleared, the port is disabled. When enabled, the 
port can transition between the on, partial, and slumber states and can detect devices. 
When disabled, the port is in the off state and cannot detect any devices. This bit takes 
precedence over P0CMD.SUD. Note: The recommendation for software code that intends 
to clear all PCS.PxE bits that are previously 1 to 0 and then to 1 again immediately shall 
refer to the polling requirement as described in P0P register bit. At any time that BIOS 
or software is clearing PCS.PxE from 1 to 0, due to time needed for port staggering 
hardware process (up to 2 ports) to complete, BIOS and software shall delay the write 
to set the TM.PCD register by 1.4us.
Bit 
Range
Default & 
Access
Description
Type: 
PCI Configuration Register
(Size: 32 bits)
TM: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
PCD
RS
VD0
Bit 
Range
Default & 
Access
Description
31:26
0h
RO
Reserved (RSVD): 
Reserved.
25:24
0h
RW
Port Clock Disable (PCD): 
When any of these bits is set to 1, the backbone clock 
driven to the associated port logic is gated and will not toggle. When this bit is cleared 
to 0, all clocks to the associated port logic will operate normally.
23:0
0b
RO
RSVD0: 
Reserved
Type: 
PCI Configuration Register
(Size: 32 bits)
SATAGC: