Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1947
17.5.38
SATA Initialization Register Index (SIRI)—Offset A0h
Access Method
Default: 00h
17.5.39
SATA Initialization Register Data (SIRD)—Offset A4h
Access Method
Default: 00000000h
17.5.40
Serial ATA Capability Register 0 (SATACR0)—Offset A8h
This register shall be read-only 0 when CC.SCC is 01h. Note that the SATACR0.NEXT is
not changed from RO to become RWO because there is an existing method
(SATAGC.FLRCSSEL bit) to bypass the FLR Capability structure. And FLR Capability
ID.NEXT is already indicating end of capability structure, it does not need change to be
RWO.
Access Method
Default: 00100012h
Type:
PCI Configuration Register
(Size: 8 bits)
SIRI:
7
4
0
0
0
0
0
0
0
0
0
IDX
RSV
D
0
Bit
Range
Default &
Access
Description
7:2
00h
RW
Index (IDX):
6-bit index pointer into the 256-byte space. Data is written into the SIRD
register and read from the SIRD register. This point to a DWord register. The byte
enables on the SIRD register affect what will be written. Note that this 256-byte register
space setting is applicable to all ports in both SATA controllers 1 and 2 (if supported).
Refer to SATA Initialization Register section for detail of the register space.
1:0
0b
RO
RSVD0:
Reserved
Type:
PCI Configuration Register
(Size: 32 bits)
SIRD:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DT
A
Bit
Range
Default &
Access
Description
31:0
00000000h
RW
Data (DTA):
32-bit data value that is written to the register pointed to by SIRI, or read
from the register pointed to by SIRI.
Type:
PCI Configuration Register
(Size: 32 bits)
SATACR0: