Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1948
Datasheet
17.5.41
Serial ATA Capability Register 1 (SATACR1)—Offset ACh
This register shall be read-only 0 when CC.SCC is 01h.
Access Method
Default: 00000048h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
RSVD
0
MA
JR
E
V
MINREV
NEXT
CA
P
Bit
Range
Default &
Access
Description
31:24
0b
RO
RSVD0:
Reserved
23:20
1h
RO
Major Revision (MAJREV):
Major revision number of the SATA Capability Pointer
implemented.
19:16
0h
RO
Minor Revision (MINREV):
Minor revision number of the SATA Capability Pointer
implemented.
15:8
00h
RW/L
Next Capability Pointer (NEXT):
00h indicating the final item in the Capability List.
The RW/L register attribute allows for flexibility in determining the capability structure
available in this PCI function. Refer to SATAGC.REGLOCK description in order to lock the
register to become RO.
7:0
12h
RO
Capability ID (CAP):
The value of 12h has been assigned by the PCI SIG to designate
the SATA Capability pointer.
Type:
PCI Configuration Register
(Size: 32 bits)
SATACR1:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
RS
VD0
BAROFS
T
BA
RL
OC
Bit
Range
Default &
Access
Description
31:16
0b
RO
RSVD0:
Reserved
15:4
004h
RO
BAR Offset (BAROFST):
Indicates the offset into the BAR where the AHCI Index/Data
pair are located (in Dword granularity). The Index and Data I/O registers are located at
offset 10h within the I/O space defined by LBAR (BAR4). A value of 004h indicates offset
10h. 000h = 0h offset; 001h = 4h offset; 002h = 8h offset; 003h = Ch offset; 004h =
10h offset ... FFFh = 3FFFh offset (max 16 KB)
3:0
8h
RO
BAR Location (BARLOC):
Indicates the absolute PCI Configuration Register address of
the BAR containing the Index/Data pair (in Dword granularity). The Index and Data I/O
registers reside within the space defined by LBAR (BAR4) in the SATA controller. A value
of 8h indicates offset 20h, which is LBAR (BAR4). 0000 - 0011b = reserved; 0100b =
10h =) BAR0; 0101b = 14h =) BAR1; 0110b = 18h =) BAR2; 0111b = 1Ch =) BAR3;
1000b = 20h =) LBAR; 1001b = 24h =) BAR5; 1010 - 1110b = reserved; 1111b =
Index/Data pair in PCI Configuration space which is not supported.