Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1950
Datasheet
17.5.45
BIST FIS Control/Status (BFCS)—Offset E0h
Access Method
Default: 00000000h
17.5.46
BIST FIS Transmit Data 1 (BFTD1)—Offset E4h
Access Method
Bit
Range
Default &
Access
Description
31:0
0h
RW
Data (DT):
This is a read/write register that is available for software to use. No
hardware action is taken on this register.
Type:
PCI Configuration Register
(Size: 32 bits)
BFCS:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
0
BF
S
BFF
P1BFI
P0BFI
BFP
RSV
D
1
Bit
Range
Default &
Access
Description
31:12
0b
RO
RSVD0:
Reserved
11
0h
RW
BIST FIS Successful (BFS):
This bit is set any time that a BIST FIS transmitted by the
SATA controller receives an R_OK completion status from the device
10
0h
RW
BIST FIS Failed (BFF):
This bit is set any time that a BIST FIS transmitted by the
SATA controller receives an R_ERR completion status from the device
9
0h
RW
Port 1 BIST FIS Initiate (P1BFI):
When a rising edge is detected on this bit, the
SATA controller will initiate a BIST FIS to the device on port 1, using the parameters
specified in this register and BFTD1 and BFTD2. The BIST FIS will only be initiated if a
device is present and not in the partial or slumber states. After a BIST FIS is
successfully completed, software must disable and re-enable PCS.P1E prior to
attempting additional BIST FISes or to return the SATA controller to a normal
operational mode. If the BIST FIS fails, as indicated by BFF in this register, software can
clear and then set this bit to initiate another BIST FIS.
8
0h
RW
Port 0 BIST FIS Initiate (P0BFI):
When a rising edge is detected on this bit, the
SATA controller will initiate a BIST FIS to the device on port 0, using the parameters
specified in this register and BFTD1 and BFTD2. The BIST FIS will only be initiated if a
device is present and not in the partial or slumber states. After a BIST FIS is
successfully completed, software must disable and re-enable PCS.P0E prior to
attempting additional BIST FISes or to return the SATA controller to a normal
operational mode. If the BIST FIS fails, as indicated by BFF in this register, software can
clear and then set this bit to initiate another BIST FIS.
7:2
0h
RW
BIST FIS Parameters (BFP):
These bits form the contents of the upper 6 bits of the
BIST FIS Pattern Definition in the BIST FIS transmitted by the SATA controller. This field
is not port specific - its contents will be used for any BIST FIS initiated on the SATA
controller. The specific bit definitions are: Bit 7 (T) Far End Transmit mode; bit 6 (A)
Align Bypass mode; bit 5 (S) Bypass Scrambling; bit 4 (L) Far End Retimed Loopback;
bit 3 (F) Far End Analog Loopback; bit 2 (P) Primitive bit for use with Transmit mode.
1:0
0b
RO
RSVD1:
Reserved
Type:
PCI Configuration Register
(Size: 32 bits)
BFTD1: