Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1954
Datasheet
17.6.2
Primary Status (PSTS)—Offset 2h
Access Method
Default: 00h
17.6.3
Primary Descriptor Table Pointer (PDTP)—Offset 4h
Access Method
Default: 00000000h
Type:
I/O Register
(Size: 8 bits)
PSTS:
LBAR Type:
PCI Configuration Register (Size: 32 bits)
LBAR Reference:
[B:0, D:19, F:0] + 20h
7
4
0
0
0
0
0
0
0
0
0
S
D1DC
D0DC
RSV
D
0
I
ER
R
AC
T
Bit
Range
Default &
Access
Description
7
0h
RO
Simplex Only (S):
This read-only bit indicates whether or not I both bus master
channels (primary and secondary) can be operated at the same time. If the bit is a 0,
then the channels operate independently and can be used at the same time. If the bit is
a 1, then only one channel may be used at a time.
6
0h
RW
Device 1 DMA Capable (D1DC):
A scratchpad bit set by SW to indicate that device 1
of this channel is capable of DMA transfers. This bit has no effect on the hardware.
5
0h
RW
Device 0 DMA Capable (D0DC):
A scratchpad bit set by SW to indicate that device 0
of this channel is capable of DMA transfers. This bit has no effect on the hardware.
4:3
0b
RO
RSVD0:
Reserved
2
0h
RW/1C
Interrupt (I):
This bit is set when a device FIS is received with the I bit has been set
provided that software has not disabled interrupt via the nIEN bit of Device Control
Register.
1
0h
RW/1C
Error (ERR):
This bit is set when the controller encounters an error during the transfer
and must stop the transfer. See Error Handling for the list of errors that set this bit.
0
0h
RO
Active (ACT):
Set by the host when the START bit is written to the Command register,
and cleared by the host when the last transfer for a region is performed, where EOT for
that region is set in the region descriptor, and when the START bit is cleared in the
Command register and the controller has returned to an idle condition.
Type:
I/O Register
(Size: 32 bits)
PDTP:
LBAR Type:
PCI Configuration Register (Size: 32 bits)
LBAR Reference:
[B:0, D:19, F:0] + 20h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DBA
RSVD
0