Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1955
17.6.4
Secondary Command (SCMD)—Offset 8h
Access Method
Default: 00h
17.6.5
Secondary Status (SSTS)—Offset Ah
Access Method
Default: 00h
Bit
Range
Default &
Access
Description
31:2
00000000h
RW
Descriptor Base Address (DBA):
Corresponds to A[31:2]. This table must not cross a
64K boundary in memory. When read, the current value of the pointer is returned
1:0
0b
RO
RSVD0:
Reserved
Type:
I/O Register
(Size: 8 bits)
SCMD:
LBAR Type:
PCI Configuration Register (Size: 32 bits)
LBAR Reference:
[B:0, D:19, F:0] + 20h
7
4
0
0
0
0
0
0
0
0
0
RS
VD0
RWC
RS
VD1
ST
A
R
T
Bit
Range
Default &
Access
Description
7:4
0b
RO
RSVD0:
Reserved
3
0h
RW
Read / Write Control (RWC):
Sets the direction of the bus master transfer: 0 =
memory to device, 1 = device to memory. This bit must not be changed when the bus
master function is active.
2:1
0b
RO
RSVD1:
Reserved
0
0h
RW
Start/Stop Bus Master (START):
Setting this bit enables bus master operation of the
controller. Bus master operation does not actually start unless the Bus Master Enable bit
in PCI configuration space is also set. Clearing it halts bus master operation.
Type:
I/O Register
(Size: 8 bits)
SSTS:
LBAR Type:
PCI Configuration Register (Size: 32 bits)
LBAR Reference:
[B:0, D:19, F:0] + 20h
7
4
0
0
0
0
0
0
0
0
0
S
D1DC
D0DC
RSV
D
0
I
ER
R
AC
T