Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1956

Datasheet

Default: 00000000h

7

0h

RO

This read-only bit indicates whether or not I both bus master 

channels (primary and secondary) can be operated at the same time. If the bit is a 0, 

then the channels operate independently and can be used at the same time. If the bit is 

a 1, then only one channel may be used at a time.

6

0h

RW

A scratchpad bit set by SW to indicate that device 1 

of this channel is capable of DMA transfers. This bit has no effect on the hardware.

5

0h

RW

A scratchpad bit set by SW to indicate that device 0 

of this channel is capable of DMA transfers. This bit has no effect on the hardware.

4:3

0b

RO

Reserved

2

0h

RW/1C

This bit is set when a device FIS is received with the I bit has been set 

provided that software has not disabled interrupt via the nIEN bit of Device Control 

Register.

1

0h

RW/1C

This bit is set when the controller encounters an error during the transfer 

and must stop the transfer. See Error Handling for the list of errors that set this bit.

0

0h

RO

Set by the host when the START bit is written to the Command register, 

and cleared by the host when the last transfer for a region is performed, where EOT for 

that region is set in the region descriptor, and when the START bit is cleared in the 

Command register and the controller has returned to an idle condition.

I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:19, F:0] + 20h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DBA

RSV

D

0

31:2

00000000h

RW

Corresponds to A[31:2]. This table must not cross a 

64K boundary in memory. When read, the current value of the pointer is returned

1:0

0b

RO

Reserved