Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1963
25
1h
RW/O
Supports Activity LED (SAL):
Indicates the S-ATA controller supports a single output
pin (SATALED#) which indicates activity.
24
1h
RW/O
Supports Command List Override (SCLO):
When set to 1, indicates that the HBA
supports the PxCMD.CLO bit and its associated function. When cleared to 0, The HBA is
not capable of clearing the BSY and DRQ bits in the Status register in order to issue
software reset if these bits are still set from a previous operation.
23:20
2h
RW/O
Interface Speed Support (ISS):
Indicates the maximum speed the S-ATA controller
can support on its ports. These encodings match the system software programmable
PxSCTL.DET.SPD field. 0000 = Reserved; 0001 = Gen 1 (1.5 Gbps); 0010 = Gen 2 (3
Gbps); 0011 = Gen 3 (6 Gbps); 0100 - 1111 = Reserved.
19
0h
RO
Supports Non-Zero DMA Offsets (SNZO):
Reserved as per AHCI 1.3
18
0h
RW/O
Supports AHCI mode only (SAM):
The SATA controller may optionally support AHCI
access mechanism only. A value of 0 indicates that in addition to the native AHCI
mechanism (via ABAR), the SATA controller implements a legacy, task-file based
register interface such as SFF-8038i. A value of 1 indicates that the SATA controller does
not implement a legacy, task-file based register interface.
17
0h
RO
Supports Port Multiplier (SMP):
Not supported.
16
0h
RO
FIS-based Switching Supported (FBSS):
Not supported.
15
1h
RO
PIO Multiple DRQ Block (PMD):
If set to 1, the HBA supports multiple DRQ block data
transfers for the PIO command protocol.
14
1h
RW/O
Slumber State Capable (SSC):
The SATA controller supports the slumber state.
13
1h
RW/O
Partial State Capable (PSC):
The SATA controller supports the partial state.
12:8
1Fh
RO
Number of Command Slots (NCS):
1Fh indicating support for 32 slots.
7
0h
RO
Command Completion Coalescing Supported (CCCS):
When set to 1, indicates that
the HBA supports command completion coalescing. When command completion
coalescing is supported, the HBA has implemented the CCC_CTL and the CCC_PORTS
global HBA registers. When cleared to 0, indicates that the HBA does not support
command completion coalescing and the CCC_CTL and CCC_PORTS global HBA registers
are not implemented.
6
0h
RO
Enclosure Management Supported (EMS):
Not supported
5
0h
RW/O
Supports External SATA (SXS):
When set to 1, indicates that the HBA has one or
more Serial ATA ports that has a signal only connector that is externally accessible. If
this bit is set, software may refer to the PxCMD.ESP bit to determine whether a specific
port has its signal connector externally accessible as a signal only connector (i.e. power
is not part of that connector). When the bit is cleared to 0, indicates that the HBA has no
Serial ATA ports that have a signal only connector externally accessible.
4:0
02h
RO
Number of Ports (NP):
0's based value indicating the maximum number of ports
supported. Note that the number of ports indicated in this field may be more than the
number of ports indicated in the PI register. Number of ports shall be dependent on
MAP.SC and PCIe/SATA muxing configuration where if ANY of these parameter disable a
particular port then that port is disabled and not counted. The maximum number of
ports supported by SIP is 2 and the least is 0 (i.e. Function Disable). In the case of 0
port configuration, the value of NP is a don't care (while implementation has it fixed as
07h). Any combination in between is supported by SATA host controller. Indicates the
number of supported ports.
Bit
Range
Default &
Access
Description