Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1971
17.8.12
Port-Command List Base Address (PxCLB0)—Offset 100h
Access Method
Default: 00000000h
17.8.13
Port-Command List Base Address Upper 32-bits (PxCLBU0)—
Offset 104h
Access Method
Default: 00000000h
1
1h
RW/O
R1:
If set to 1, then RAID1 is enabled
0
1h
RW/O
R0:
If set to 1, then RAID0 is enabled
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CLB
RS
VD0
Bit
Range
Default &
Access
Description
31:10
000000h
RW
Command List Base Address (CLB):
Indicates the 32-bit base for the command list
for this port. This base is used when fetching commands to execute. This address must
be 1K aligned as indicated by bits 31:10 being read/write. Note that these bits are not
reset on a HBA reset.
9:0
0b
RO
RSVD0:
Reserved
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxCLBU0:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CLBU
Bit
Range
Default &
Access
Description
31:0
00000000h
RW
Command List Base Address Upper (CLBU):
Indicates the upper 32-bits for the
command list base address for this port. This base is used when fetching commands to
execute. Note that these bits are not reset on a HBA reset.