Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1975
6
0h
RW
Port Change Interrupt Enable (PCE):
When set, GHC.IE is set, and P0IS.PCS is set,
the HBA shall generate an interrupt.
5
0h
RW
Descriptor Processed Interrupt Enable (DPE):
When set, GHC.IE is set, and
P0IS.DPS is set, the HBA shall generate an interrupt.
4
0h
RW
Unknown FIS Interrupt Enable (UFE):
When set, GHC.IE is set, and PxIS.UFS is set
to 1, the HBA shall generate an interrupt.
3
0h
RW
Set Device Bits FIS Interrupt Enable (SDBE):
When set, GHC.IE is set, and
P0IS.SDBS is set, the HBA shall generate an interrupt.
2
0h
RW
DMA Setup FIS Interrupt Enable (DSE):
When set, GHC.IE is set, and P0IS.DSS is
set, the HBA shall generate an interrupt.
1
0h
RW
PIO Setup FIS Interrupt Enable (PSE):
When set, GHC.IE is set, and P0IS.PSS is
set, the HBA shall generate an interrupt.
0
0h
RW
Device to Host Register FIS Interrupt Enable (DHRE):
When set, GHC.IE is set,
and P0IS.DHRS is set, the HBA shall generate an interrupt.
Bit
Range
Default &
Access
Description