Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1977

24

0h

RW

When set, the connected device is an ATAPI device. This bit 

is used by the HBA to control whether or not to generate the desktop LED when 

commands are active.

23

0h

RW

When set to 1, the 

HBA may perform Automatic Partial to Slumber Transitions. When cleared to 0 - the port 

shall not perform Automatic Partial to Slumber Transitions. Software shall only set this 

bit to 1 - if CAP2.APST is set to 1; if CAP2.APST is cleared to 0 - software shall treat this 

bit as reserved.

22

0h

RO

The SATA controller does not support 

FIS-Based Switching.

21

0h

RW/O

When set to 1, indicates that this port is routed externally 

and will be used with an external SATA device. When set to 1, CAP.SXS must also be set 

to 1. When cleared (0), indicates that this port is not routed externally and supports 

internal SATA devices only. If ESP is set to 1, then the port may experience hot plug 

events.

20

0h

RO

The SATA controller does not support cold presence 

detect.

19

0h

RW/O

If set to 1, the platform 

supports a mechanical presence switch attached to this port. If cleared to 0, the 

platform does not support a mechanical presence switch attached to this port.

18

0h

RW/O

This indicates whether this port is connected to a 

device which can be hot plugged. SATA by definition is hot-pluggable, but not all 

platforms are constructed to allow the device to be removed (it may be screwed into the 

chassis, for example). This bit can be used by system software to indicate a feature 

such as eject device to the end-user.

17

0h

RO

Not supported

16

0b

RO

Reserved

15

0h

RO

When this bit is set it indicates that the command list 

DMA engine for the port is running.

14

0h

RO

When this bit is set it indicates that the FIS Receive DMA 

engine for the port is running.

13

0h

RO

The MPSS bit reports the state of a 

mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the 

mechanical presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set to 1 

and the mechanical presence switch is open then this bit is set to 1. If CAP.SMPS is set 

to 0 then this bit is cleared to 0. Software should only use this bit if both CAP.SMPS and 

PxCMD.MPSP are set to 1.

12:8

00h

RO

Indicates the current command slot the HBA is 

processing. This field is valid when the PxCMD.ST bit is set, and is constantly updated by 

the HBA. This field can be updated as soon as the HBA recognizes an active command 

slot, or at some point soon after when it begins processing the command. When 

PxCMD.ST transitions from a 1 to a 0, the HBA will reset this field to 0. After PxCMD.ST 

transitions from 0 to 1, the highest priority slot to issue from next is command slot 0. 

After the first command has been issued, the highest priority slot to issue from next is 

PxCMD.CCS + 1. For example, after the HBA has issued its first command, if 

PxCMD.CCS = 0h and PxCI is set to 3h, the next command that will be issued is from 

command slot 1.

7

0b

RO

Reserved

6

0h

RO

If set to 1, the platform supports PHYSLP on this port. If 

cleared to 0, the platform does not support PHYSLP on this port. This bit may only be set 

to 1 if CAP2.SPS is set to 1.