Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1978

Datasheet

Default: 0000007Fh

5

0h

RW

This bit is read/write for HBAs that support 

aggressive PHYSLP management (CAP2.SAPM == 1). This bit is read-only for HBAs that 

do not support aggressive PHYSLP management (CAP2.SPS == 0). When this bit is set 

to 1, the HBA shall assert the PHYSLP signal after the port has been idle (PxCI == 0h 

and PxSACT == 0h) for the amount of time specified by the GHC.PITO register. When 

this bit is cleared to 0, the HBA does not enter PHYSLP unless software directed via 

PxCMD.ICC. This bit shall only be set to 1 if PxCMD.PSP is set to 1. If this bit is set to 1 

and software clears the bit to 0, then the HBA shall de-assert the PHYSLP signal if 

asserted.

4

0h

RW

When set, the HBA may post received FISes into the FIS 

receive area pointed to by PxFB and PxFBU. When cleared, received FISes are not 

accepted by the HBA, except for the first D2H register FIS after the initialization 

sequence.

3

0h

RW/1S

Setting this bit to 1 causes PxTFD.STS.BSY and 

PxTFD.STS.DRQ to be cleared to 0. This allows a software reset to be transmitted to the 

device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS 

register. The HBA sets this bit to 0 when PxTFD.STS.BSY and PxTFD.STS.DRQ have been 

cleared to 0. A write to this register with a value of 0 shall have no effect.

2

1h

RO

The SATA controller does not support cold presence detect.

1

0h

RW

This bit is read/write for HBAs that support staggered spin-up 

via CAP.SSS. This bit is read only 1 for HBAs that do not support staggered spin-up. On 

an edge detect from 0 to 1, the HBA shall start a COMRESET initialization sequence to 

the device. Clearing this bit causes no action on the interface. Clearing this bit to0 does 

not cause any OOB signal to be sent on the interface. When this bit is cleared to 0 and 

PxSCTL.DET = 0h, the HBA will enter listen mode.

0

0h

RW

When set, the HBA may process the command list. When cleared, the HBA 

may not process the command list. Whenever this bit is changed from a 0 to a 1, the 

HBA starts processing the command list at entry 0. Whenever this bit is changed from a 

1 to a 0, the PxCI and PxSACT register is cleared by the HBA upon the HBA putting the 

controller into an idle state. PxTFD shall be updated also.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:19, F:0] + 24h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

RSV

D

0

ER

R

STS

_

B

S

Y

STS

_

R

S

VD

0

ST

S_DRQ

STS

_

R

S

VD

1

ST

S_E

R

R

31:16

0b

RO

Reserved

15:8

00h

RO

Contains the latest copy of the task file error register.