Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1981

Default: 00000000h

7:4

0h

RW

Indicates the highest allowable speed of the interface. 0h No 

speed negotiation restrictions. 1h Limit speed negotiation to Generation 1 

communication rate. 2h Limit speed negotiation to a rate not greater than Generation 2 

communication rate. 3h Limit speed negotiation to a rate not greater than Generation 3 

communication rate. All other values reserved. Note: If software changes SPD after port 

has been enabled, software is required to perform a port reset via DET=1h.

3:0

0h

RW

Controls HBA's device detection and interface 

initialization. 0h No device detection or initialization action requested. 1h Perform 

interface communication initialization sequence to establish communication. This is 

functionally equivalent to a hard reset and results in the interface being reset and 

communications reinitialized. While this field is 1h, COMRESET is continuously 

transmitted on the interface. Software should leave the DET field set to 1h for a 

minimum of 1 millisecond to ensure that a COMRESET is sent on the interface. 4h 

Disable the Serial ATA interface and put Phy in offline mode. All other values reserved. 

This field may only be changed when PxCMD.ST is '0'. Changing this field while the HBA 

is running results in undefined behavior. When PxCMD.ST is set to '1', this field should 

have a value of 0h. It is permissible to implement any of the Serial ATA defined 

behaviors for transmission of COMRESET when PxSCTL.DET = 1h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:19, F:0] + 24h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DIAG

ERR

31:16

0000h

RW/1C

Contains diagnostic error information for use by diagnostic 

software in validating correct operation or isolating failure modes. Bit Field 31:27 

Reserved 26 Exchanged (X): When set to one this bit indicates that a change in device 

presence has been detected since the last time this bit was cleared. The means by which 

the implementation determines that the device presence has changed is vendor specific. 

This bit shall always be set to one anytime a COMINIT signal is received. This bit is 

reflected in the P0IS.PCS bit. 25 Unrecognized FIS Type (F): Indicates that one or more 

FISs were received by the Transport layer with good CRC, but had a type field that was 

not recognized. 24 Transport state transition error (T): Indicates that an error has 

occurred in the transition from one state to another within the Transport layer since the 

last time this bit was cleared. 23 Link Sequence Error (S): Indicates that one or more 

Link state machine error conditions were encountered. The Link Layer state machine 

defines the conditions under which the link layer detects an erroneous transition. 22 

Handshake Error (H): Indicates that one or more R_ERR handshake response was 

received in response to frame transmission. Such errors may be the result of a CRC 

error detected by the recipient, a disparity or 8b/10b decoding error, or other error 

condition leading to a negative handshake on a transmitted frame. 21 CRC Error (C): 

Indicates that one or more CRC errors occurred with the Link Layer. 20 Disparity Error 

(D): This field is not used by AHCI. 19 10B to 8B Decode Error (B): Indicates that one or 

more 10B to 8B decoding errors occurred. 18 Comm Wake (W): Indicates that a Comm 

Wake signal was detected by the Phy. 17 Phy Internal Error (I): Indicates that the Phy 

detected some internal error. 16 PhyRdy Change (N): When set to 1 this bit indicates 

that the internal PhyRdy signal changed state since the last time this bit was cleared. 

The state of this bit is reflected in the PxIS.PRCS interrupt status bit and an interrupt 

will be generated if enabled.