Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1992
Datasheet
17.8.36
Port-Serial ATA Status (PxSSTS1)—Offset 1A8h
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxSSTS1:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
0
IPM
SP
D
DE
T
Bit
Range
Default &
Access
Description
31:12
0b
RO
RSVD0:
Reserved
11:8
0h
RO
Interface Power Management (IPM):
Indicates the current interface state 0h =
Device not present or communication not established. 1h = Interface in active state. 2h
= Interface in PARTIAL power management state. 6h = Interface in SLUMBER power
management state. 8h = PHYSLP asserted. All other values reserved. This field reflects
the interface power management state for both device and host initiated power
management. Note: If an automatic partial to slumber transition occurs, PxSSTS.IPM
shall reflect that the host has entered slumber (PxSSTS.IPM = 6h.)
7:4
0h
RO
Current Interface Speed (SPD):
Indicates the negotiated interface communication
speed. 0h = Device not present or communication not established. 1h = Generation 1
communication rate negotiated. 2h = Generation 2 communication rate negotiated. 3h
= Generation 3 communication rate negotiated. All other values reserved
3:0
0h
RO
Device Detection (DET):
Indicates the interface device detection and Phy state. 0h =
No device detected and Phy communication not established. 1h = Device presence
detected but Phy communication not established. 3h = Device presence detected and
Phy communication established. 4h = Phy in offline mode as a result of the interface
being disabled or running in a BIST loopback mode. All other values reserved. Note that,
while the true reset default value of this register is 0h, the value read from this register
depends on drive presence and the point in time within the initialization process when
the register is read. Note: The means by which the implementation determines device
presence may be vendor specific. However, device presence shall always be indicated
anytime a COMINIT signal is received.