Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1993
17.8.37
Port-Serial ATA Control (PxSCTL1)—Offset 1ACh
Access Method
Default: 00000000h
17.8.38
Port-Serial ATA Error (PxSERR1)—Offset 1B0h
Access Method
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
PxSCTL1: 
ABAR Type: 
PCI Configuration Register (Size: 32 bits)
ABAR Reference: 
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
0
PM
P
SP
M
IPM
SP
D
DE
T
Bit 
Range
Default & 
Access
Description
31:20
0b
RO
RSVD0: 
Reserved
19:16
0h
RW
Port Multiplier Port (PMP): 
This field is not used by AHCI.
15:12
0h
RW
Select Power Management (SPM): 
This field is not used by AHCI.
11:8
0h
RW
Interface Power Management Transitions Allowed (IPM): 
Indicates which power 
states the HBA is allowed to transition to. If an interface power management state is not 
allowed via this register field, the HBA will not initiate that state and the HBA will 
PMNAKP any request from the device to enter that state. 0h No interface restrictions 1h 
Transitions to the PARTIAL state disabled 2h Transitions to the SLUMBER state disabled 
3hTransitions to both PARTIAL and SLUMBER states disabled 4h Transitions to the 
DEVSLP power management state are disabled 5h Transitions to the Partial and DEVSLP 
power management states are disabled 6h Transitions to the Slumber and DEVSLP 
power management states are disabled 7h Transitions to the Partial, Slumber and 
DEVSLP power management states are disabled All other values reserved
7:4
0h
RW
Speed Allowed (SPD): 
Indicates the highest allowable speed of the interface. 0h No 
speed negotiation restrictions. 1h Limit speed negotiation to Generation 1 
communication rate. 2h Limit speed negotiation to a rate not greater than Generation 2 
communication rate. 3h Limit speed negotiation to a rate not greater than Generation 3 
communication rate. All other values reserved. Note: If software changes SPD after port 
has been enabled, software is required to perform a port reset via DET=1h.
3:0
0h
RW
Device Detection Initialization (DET): 
Controls HBA's device detection and interface 
initialization. 0h No device detection or initialization action requested. 1h Perform 
interface communication initialization sequence to establish communication. This is 
functionally equivalent to a hard reset and results in the interface being reset and 
communications reinitialized. While this field is 1h, COMRESET is continuously 
transmitted on the interface. Software should leave the DET field set to 1h for a 
minimum of 1 millisecond to ensure that a COMRESET is sent on the interface. 4h 
Disable the Serial ATA interface and put Phy in offline mode. All other values reserved. 
This field may only be changed when PxCMD.ST is '0'. Changing this field while the HBA 
is running results in undefined behavior. When PxCMD.ST is set to '1', this field should 
have a value of 0h. It is permissible to implement any of the Serial ATA defined 
behaviors for transmission of COMRESET when PxSCTL.DET = 1h