Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2021
17.17.3
PCS_DWORD2 (pcs_dword2)—Offset 8h
Access Method
Default: 00000000h
5
1h
RW
soft_reset_n:
Active low soft reset override
4
0h
RW
reg_diginelben:
Override for near end digital loopback.
3
0h
RW
reg_digifelben:
Override for far end digital loopback
2
0h
RW
reg_strapgroup_ovrden:
Override Enable for Strap Group
1
0h
RW
reg_yank_timer_done_b_ovrd:
Override for yank_timer_done_b
0
0h
RW
reg_yank_timer_done_b_ovrd_en:
Override Enable for yank_timer_done_b
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword2:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_rxpwrfsm_pibiasoff_de
la
y_3_0
cr
i_sqdbe
xitti
m
er_o
verride
_3_0
cri
_
sq
dbentryti
m
er_o
ve
rride
_5_0
reg_rx
dr
cgtsqs
el
_1_0
cr
i_reut_Sla
ve
Side
DataC
h
ec
kingEn
cr
i_sqd
b
time
r_o
vre
n
cr
i_rxpwrfs
m
_time
r_o
vre
n
re
g_rxidle
cr
i_rxr
awdata_sel
cr
i_dyn
kalign
_
ec
o330
2703_mode
cr
i_dynkal
ign_eco3302703_o
vren
re
g_rxp
w
rfsm_pib
iasoff_o
vr
ride
cr
i_reset_kalignlck
cr
i_eb
ptrr
st
cri_c
o
mdispfix
cri_forcebankhit
cri
_
kal
ignmode
_1_0
cri_skp
p
ro
cd
is
cri_e
lastic
b
uffe
r_maskd
is
Bit
Range
Default &
Access
Description
31:28
0h
RW
reg_rxpwrfsm_pibiasoff_delay_3_0:
Override value for delay (in 2ns increments)
between deassertion of opianclkbufen and opibiasen
27:24
0h
RW
cri_sqdbexittimer_override_3_0:
Rx squelch exit debounce timer
23:18
0h
RW
cri_sqdbentrytimer_override_5_0:
Rx squelch entry debounce timer
17:16
0h
RW
reg_rxdrcgtsqsel_1_0:
Squelch output select