Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2022

Datasheet

Default: 5515ACAAh

15

0h

RW

Enable REUT slave side checking while in 

loopback slave

14

0h

RW

Squelch debounce timer override enable

13

0h

RW

Rx power management fsm timer override enable

12

0h

RW

Chicken bit to override i_rxidle from controller and keep Rx in P0 or P0s

11

0h

RW

When asserted bypass K-align, 10b/8b decoder and Elastic buffer

10

0h

RW

Kalign Mode Override Value When 

cri_dynkalign_eco3302703_ovren is set, this value selects kalignmode 0 - use register 

bits cri_kalignmode[1:0] to select kalignmode 1 - select the 4 COM kalign mode'

9

0h

RW

Kalign Mode Override Enable Overrides kalign 

mode select pin, allowing config bit kalignmode_override_val to select kalignmode.

8

0h

RW

When asserted selects 

reg_rxpwrfsm_pibiasoff_delay[3:0]

7

0h

RW

When asserted resets Kalign lock indication and Kalign is 

performed again. The conditions when this would assert includes and is not restricted to 

any power management states (L0s, L1) or polling quiet states etc.

6

0h

RW

Global broadcast to all lanes that the Elastic Buffer pointers should be 

reset. This is a pulse and will be generated when we need to reset the pointers because 

of collision or various other reasons.

5

0h

RW

Chicken bit to force disparity in dynamic K-align mode

4

0h

RW

Chicken bit to enable data appear on NOA post k-align lock 

although k-align block is not achieving lock. This is only for NOA observeability and not 

for other purpose

3:2

0h

RW

KALIGN Mode Select 00 = dynamic kalign all the time. 

Accounts for bit slips on incoming stream which can cause symbol to be detected on 

different bank 10 = dynamic kalign up to L0 x1 = static kalign (same as GDG). 

Assumes symbol always detected on same data bank

1

0h

RW

SKIP Ordered-Set Processing Disable When this configuration bit is 

asserted, then SKIP ordered=sets will be ignored (in EB block). Used in Elastic buffer 

block. 0 = Normal operation. SKIP ordered=sets will be processed by the Elastic Buffer 

1 = SKIP processing disabled.

0

0h

RW

Config bit (chicken bit) to disable the masking logic after 

elec idle ordered set is seen

Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write