Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2024

Datasheet

Default: 00003E63h

7:0

C1h

RW

Pattern Buffer Storage See cri_dfx_patbuf[7:0] description.

Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1

cri

_

dfx_patbuftr

ain

cr

i_dfx_pr

bspoly_2_0

cri_dfx_

patbu

fsiz

e_1_0

cri_d

fx_patb

ufloop

cri_d

fx_patb

ufdw

id

th

cr

i_

df

x_

pa

tb

uf

tr

ai

nov

r

cr

i_dfx_marginmode

cr

i_

d

fx

_

ch

k_

se

l

cri_d

fx_patc

hk

en

cr

i_d

fx_patg

en

en

cri_d

fx_

cl

re

rrc

nt

cr

i_dfx_lc

er

eset

cr

i_dfx_lc

es

ta

rt

cr

i_dfx_pat

b

uf_7_0

cr

i_dfx_patbuf_15_8

31

0h

RW

Pattern Buffer Manual Training When DFXPATBUFTRAINOVR and 

DFXLCESTART are asserted, this manually controls whether the Pattern Buffers are in 

training or have completed training. 0 : Send training patterns (default) 1 : Send 

contents of DFXPATBUF

30:28

0h

RW

PRBS Polynomial Select the polynomial to be used by the 

PRBS in the Pattern Generator and Pattern Checker. PRBS support 10b or 8b, which is 

indicated by the msb. 000 - x^16 + x^5 + x^4 + x^3 + 1 (USB3/PCIe Scrambler) (8b) 

001 - x^16 + x^15 + x^13 + x^4 + 1 (SATA scrambler) (8b) 010 - x^31 + x^28 + 1 

(8b) 011 - x^7 + x^6 + 1 (8b) 100 - x^15 + x^14 + 1 (10b) 101 - x^23 + x^18 + 1 

(10b) 110 - x^31 + x^28 + 1 (10b) 111 - x^7 + x^6 + 1 (10b)

27:26

0h

RW

Pattern Buffer Size Select the size of the Pattern Buffer to 

use. The MSB will always be bit 79. The LSB will depend on this select and the 

DFXLCEDATAWIDTH (10b or 8b mode). 00 : full 80b buffer (Default) 01 : 70b (while in 

10b mode), 56b (while in 8b mode) 10 : 40b (while in 10b mode), 32b (while in 8b 

mode) 11 : 10b (while in 10b mode), 8b (while in 8b mode)

25

0h

RW

Pattern Buffer Looping Enable Enables looping of the Patter 

Buffer. By default, the contents of Pattern Buffer will be used once and stop. 

Alternatively, the Pattern Buffer will continue to loop until the DFXLCESTART is de-

asserted. 0 : Run Pattern Buffer only once (default) 1 : Loop Pattern Buffer until 

stopped

24

0h

RW

Pattern Buffer Data Width Selects between 10 bit or 8 bit data 

width for the Pattern Buffer. Determines where in the Tx/Rx path the data is inserted/

retrieved. 0 : 10b (default) 1 : 8b

23

0h

RW

Pattern Buffer Training Override Enables manual training of 

the Pattern Buffer instead of the automated coordination between the Pattern Checker 

and Patter Generator. When asserted, the DFXPATBUFTRAIN bit will be used to force 

when training is active and when it is complete. 0 : Automatic Training (default) 1 : 

Enable Manual Training