Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2030
Datasheet
17.17.11 PCS_DWORD10 (pcs_dword10)—Offset 28h
Access Method
Default: 00000000h
2
0h
RW
reg_txoneszeroes:
Override for i_txoneszeroes
1:0
0h
RW
reg_latencyoptim_1_0:
Override for i_latencyoptim
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword10:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_rxpwrfsm_time
r_W
AIT_RX
_P
I_CLK_3_0
re
g_rxpwrfs
m
_timer_ENAB
LE_RX_3_0
reg_rxpw
rf
sm_tim
er_RX_SQEN_3_0
re
g_rxpw
rf
sm
_t
im
er_W
AIT_RX_PIBIAS_3_0
reg_c
lk_v
alid_cnt_7_0
re
g_rxte
rm
reg
_
rxpo
larit
y
re
g_r
xe
q
tr
ain
re
g
_
rxsq
uel
che
n
cri
_
rx
pwrfsm_sq
en
tim
er
_o
vr
de
n
re
g
_
rxintflt
ren
_
ov
er
ride
re
g_rxin
tfltre
n_l
reg_c
lk_v
alid
_
cnt_o
vr
d
Bit
Range
Default &
Access
Description
31:28
0h
RW
reg_rxpwrfsm_timer_WAIT_RX_PI_CLK_3_0:
Rx Power state m/c timer value
used to enable PI clock
27:24
0h
RW
reg_rxpwrfsm_timer_ENABLE_RX_3_0:
Rx Power state m/c timer value used to
enable receivers
23:20
0h
RW
reg_rxpwrfsm_timer_RX_SQEN_3_0:
Rx Power FSM Rx Squelch Enable Timer
Override Value Affect squelch enable startup sequence during 'synchronous' squelch
startup mode. 0000 - Invalid 0001 - 1 susclk period ... 1111 - 15 susclk period
19:16
0h
RW
reg_rxpwrfsm_timer_WAIT_RX_PIBIAS_3_0:
Rx Power state m/c timer value
used to enable PI BIAS
15:8
0h
RW
reg_clk_valid_cnt_7_0:
Over ride value for clock valid delay in clock top block before
toggling phystatus.
7
0h
RW
reg_rxterm:
Override for i_rxterm
6
0h
RW
reg_rxpolarity:
Override for i_rxpolarity