Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2031
17.17.12 PCS_DWORD11 (pcs_dword11)—Offset 2Ch
Access Method
Default: 0F000000h
5
0h
RW
reg_rxeqtrain:
Override for i_rxeqtrain
4
0h
RW
reg_rxsquelchen:
Override for i_rxsquelchen
3
0h
RW
cri_rxpwrfsm_sqentimer_ovrden:
Squelch Enable Timer Override Enable Used to
override the squelch enable timer in PCS with the timer value set by the Rx Squelch
Enable timer register (reg_rxpwrfsm_timer_RX_SQEN[3:0]).
2
0h
RW
reg_rxintfltren_override:
Rx Integral Filter Override Select 0: selects i_rxintfltren_l
input pin. 1: selects reg_rxintfltren_l register
1
0h
RW
reg_rxintfltren_l:
Override for Rx integral filter enable i_rxintfltren_l
0
0h
RW
reg_clk_valid_cnt_ovrd:
Override enable for reg_clk_valid_cnt
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword11:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
se
rv
ed
505
re
se
rv
ed
506
reg_tx2_s
tagge
r_mask_4_0
i_clkb
uf_iclk
en_o
vr
d
i_c
lkbuf_q
clk
en_o
vr
d
re
se
rv
ed
503
i_c
lkbuf_tx
clkmux
en_ovr
d
re
se
rv
ed
504
re
g_tx2_cmmdis
parit
y
reg_tx1_ctr
l_o
ve
rride
reg_tx2_ctr
l_o
ve
rride
re
g_tx2_txterm_vcc_1
re
g_tx2_txterm_vcc_0
re
g_tx2_tx
d
et
rxlp
bk
re
g_tx2_tx
ele
ct
idle
re
g_tx2_tx
co
m
pliance
re
g_
tx
2
_
txo
n
es
ze
ro
es
reg_tx2_powe
rdown_1_0
o_cap
te
ste
n_h
i_
ca
p
te
st
ou
t
fuse_o
ve
rr
ide
i_
cl
kbu
f_
ibiasen_o
vr
d
reg_lan
ede
sk
ew
_str
ap_o
vr
d_______
_____
reg_lan
e_rev
erse___
_____________
_____
reg_left_txfifo_r
st_master______
_____
re
g_right_txfifo_r
st_master_____
_____
Bit
Range
Default &
Access
Description
31:30
0h
RW
reserved505:
reserved
29
0h
RW
reserved506:
reserved
28:24
Fh
RW
reg_tx2_stagger_mask_4_0:
Mask bit for lane number. Used to group lanes for
staggering. for tx2