Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2034
Datasheet
17.17.14 PCS_DWORD13 (pcs_dword13)—Offset 34h
Access Method
Default: 00000000h
17.17.15 PCS_DWORD14 (pcs_dword14)—Offset 38h
Access Method
4:0
0h
RW
reg_lanestagger_strap_4_0:
Override for lane stagger strap
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword13:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
visa_en
re
se
rv
ed
512
visa_clk_s
el
1_4_0
vis
a_lane
_
se
l1_7_0
visa_b
ypas
s
re
se
rv
ed
511
visa_clk_s
el
0_4_0
vis
a_lane
_
se
l0_7_0
Bit
Range
Default &
Access
Description
31
0h
RW
visa_en:
VISA Enable for PCS VISA logic
30:29
0h
RW
reserved512:
reserved
28:24
0h
RW
visa_clk_sel1_4_0:
VISA Clock Select for Lane1. Selects the source synchronous
clock to be used for data being sent on lane1.
23:16
0h
RW
visa_lane_sel1_7_0:
VISA Lane Select for Lane1. Selects the byte of data to be sent
out on lane0.
15
0h
RW
visa_bypass:
VISA Bypass. Allows for signals to be passed asynchronously through
VISA block. Applies to both lane0 and lane1. 0 : Flop signals in local VISA block
(default) 1 : Bypass flops in local VISA block
14:13
0h
RW
reserved511:
reserved
12:8
0h
RW
visa_clk_sel0_4_0:
VISA Clock Select for Lane0. Selects the source synchronous
clock to be used for data being sent on lane0.
7:0
0h
RW
visa_lane_sel0_7_0:
VISA Lane Select for Lane0. Selects the byte of data to be sent
out on lane0.
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword14:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write