Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2040
Datasheet
17.17.19 PCS_DWORD18 (pcs_dword18)—Offset 48h
Access Method
Default: 00008080h
11
0h
RW
lrc_rdy_pulsegen: 
LRC Ready PulseGen Generates a pulse 1 cal_clk cycle wide on the 
lrc_rdy signal to all four targets; does not recompute local Rcomp code. Values in DWD 
0x14 (*rccodes[7:0]) will be latched into targets. User must clear this bit before 
generating another pulse. Note: User should disable PM and PER. FSM can take control 
and codes can be overriden.
10:9
0h
RW
lrc_rdy_target_1_0: 
LRC Ready Pulse Target Indicates which lrc target to recompute 
when lrc_rdy_ovd is strobed 00: irefrccode 01: txrccode 10: rxtermrccode 11: 
rxvgarccode
8
0h
RW
lrc_rdy_ovd: 
LRC Ready Override Recomputes the selected local rcomp code and 
generates a pulse 1 cal_clk cycle wide on the lrc_rdy signal that is selected in bits 
[2:1]. User must clear this bit before generating another pulse. Note: User should 
disable PM and PER. FSM can take control and codes can be overriden.
7
0h
RW
rxtermpmrcen: 
PM RCOMP Enable for Rx Termination 1 - Enables the RCOMP update 
to occur while RX is in power management state if periodic RCOMP is enabled. If this bit 
is set and the PHY is not in a power management state, no update will occur. 0 - 
Disables power management qualifier to the RCOMP update; therefore RCOMP updates 
will be based on the state of the target periodic bit.
6
0h
RW
rxvgapmrcen: 
PM RCOMP Enable for Rx VGA (Same description as the RxTerm PM 
Rcomp Enable.)
5
0h
RW
txpmrcen: 
PM RCOMP Enable for Tx 1 - Enables the RCOMP update to occur while TX is 
in power management state if periodic RCOMP is enabled. If this bit is set and the PHY 
is not in a power management state, no update will occur. 0 - Disables power 
management qualifier to the RCOMP update; therefore RCOMP updates will be based on 
the state of the target periodic bit.
4
0h
RW
irefpmrcen: 
IREF PM RCOMP Enable 1 - Enables the RCOMP update to occur while TX/
RX is in the P1 or P2 (partial or slumber) power management state if periodic RCOMP is 
enabled. If this bit is set and the PHY is not in a power management state, no update 
will occur. 0 - Disables power management qualifier to the RCOMP update; therefore 
RCOMP updates will be based on the state of the target periodic bit.
3
0h
RW
rxtermperrcen: 
Periodic RCOMP Enable for Rx Termination 1 - Enables the periodic 
RCOMP update for specified block. 0 - Disables periodic RCOMP update for specified 
block.
2
0h
RW
rxvgaperrcen: 
Periodic RCOMP Enable for Rx VGA 1 - Enables the periodic RCOMP 
update for specified block. 0 - Disables periodic RCOMP update for specified block.
1
0h
RW
txperrcen: 
Periodic RCOMP Enable for Tx 1 - Enables the periodic RCOMP update for 
specified block. 0 - Disables periodic RCOMP update for specified block.
0
1h
RW
irefperrcen: 
Periodic RCOMP Enable for Iref 1 - Enables the periodic RCOMP update for 
specified block. 0 - Disables periodic RCOMP update for specified block.
Bit 
Range
Default & 
Access
Description
Type: 
Message Bus Register
(Size: 32 bits)
pcs_dword18: 
Op Codes:
0h - Read, 1h - Write