Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2058
Datasheet
17.18.13 TX_DWORD12 (tx_dword12)—Offset 30h
Access Method
Default: 00000000h
14
0h
RW
ofrccmkeeppadpen: 
Forces enabling of common-mode keeping of PadP
13
0h
RW
ofrccmkeeppadndis: 
Forces disabling of common-mode keeping of PadN
12
1h
RW
ofrccmkeeppadpdis: 
Forces disabling of common-mode keeping of PadP
11
0h
RW
omakedeeperfifo: 
Make FIFO deeper by 1 symbol clock cycle. Still not implemented. 
Implementation costs 10 flops in symb clock domain. Implementation is required for 
8bits PISO only which is in next phase of products.
10:8
0h
RW
ofrclatencyoptim_2_0: 
Changes the latency from loadgenen assertion to the 
sampling of 10bits data into fast-clock domain. The latency is determined by Fuses 
(through i_latencyoptim[1:0]) + ... 0XX =) + 0 (Not changing the latency.) 100 =) - 
4UI 101 =) - 2UI 110 =) + 2UI 111 =) + 4UI Important Note: When changing the 
latency too high or too low is will wrap-around what might cause data loss on beginning 
or end of transmitting. If you decide to plan with the latency consider changing 
'omakedeeperfifo' too
7
0h
RO
reserved536: 
reserved
6
0h
RW
ofrcrcvdtcten: 
force initiation of Tx-detect-Rx procedure
5:4
0h
RW
otxrcvdtctclkrate_1_0: 
determines the clock rate in the flash comparator. 00 - use 
sus-clock as is (25MHz in phase2) default 01 - use sus-clock by 4 10 - use sus-clock by 
2 11 - reserved In phase1 the rate was 2'b10 susfreq125MHz
3
0h
RO
reserved535: 
reserved
2
0h
RO
reserved534: 
reserved
1
0h
RO
reserved533: 
reserved
0
0h
RW
oneloopbacken: 
Near-End LoopBack enable
Bit 
Range
Default & 
Access
Description
Type: 
Message Bus Register
(Size: 32 bits)
tx_dword12: 
Op Codes:
0h - Read, 1h - Write