Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2066
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
reg_tx
cf
gch
ange_v
alid_dela
y_3_0
reg_tx
cfgc
hange
_
rs
t_dela
y_3_0
re
se
rv
ed
500
reg_tx
cfgc
hange
_
widt
h_4_0
re
g_tx
cf
gch
ange
_
ov
rrid
e
re
g_tx2_soft
_
re
se
t_n
re
g_txs
w
n
g
_clk
sel
re
g_rcvde
tect_o
vr
d
_______
____________
re
g_rcvde
tected__________
____________
reg_rc
vdete
ctfinis
he
d____
____________
re
g_rcvd
et
ect
_
puls
e_w
idth
_
ov
rd
reg_rc
vdete
ct_puls
e_
widt
h_2_0
re
g_tx1_soft
_
re
se
t_n
re
g_tx_8b
10b
_
byp
ass
reg
_
tx_lane
u
p
reg_left_txfifo_rs
t_m
as
te
r2
re
g_righ
t_txfifo_rs
t_m
as
te
r2
re
g
_
plllin
ksync
h
_o
vrd
en
re
g_
plllink
synch_ovrd
re
g_tx
1_c
m
m
dis
p
ar
ity
Bit
Range
Default &
Access
Description
31:28
0h
RW
reg_txcfgchange_valid_delay_3_0:
Controls counter to wait 128ns after
txcfgchange asserts when coming out of reset. This will control phystatus de-assertion
after reset. Note: Minimum value when programmed has to be 4'b0100 or greater.
27:24
0h
RW
reg_txcfgchange_rst_delay_3_0:
Counter value to delay txcfgchange toggle after
coming out of reset.
23
0h
RW
reserved500:
reserved
22:18
0h
RW
reg_txcfgchange_width_4_0:
Tx power fsm output - divider ratio
17
0h
RW
reg_txcfgchange_ovrride:
Override txchfchange related counters.
(reg_txcfgchange_width, reg_txcfgchange_valid_delay, reg_txcfgchange_rst_delay)
16
1h
RW
reg_tx2_soft_reset_n:
Active low reset to independently reset Tx lane2 in Display
Port
15
0h
RW
reg_txswng_clksel:
When 0 selects divide by 2 version of the ick_plllink clock for Tx
swing control logic When 1 selects ick_plllink clock for Tx swing control logic.
14
0h
RW
reg_rcvdetect_ovrd___________________:
override enable for rcvdetected and
rcvdetectfinished
13
0h
RW
reg_rcvdetected______________________:
override for rcvdetected
12
0h
RW
reg_rcvdetectfinished________________:
override for rcvdetectfinished
11
0h
RW
reg_rcvdetect_pulse_width_ovrd:
override enable for rcvdetect_pulse_width
10:8
0h
RW
reg_rcvdetect_pulse_width_2_0:
override value for rcvdetect_pusle_width
7
1h
RW
reg_tx1_soft_reset_n:
Active low reset to independently reset Tx lane1 in Display
Port 0: Lane 1 reset 1: Lane 1 active
6
0h
RW
reg_tx_8b10b_bypass:
Bypass 8b10b encoder ( for SAPIS etc interface.) 0 = Disable
8b/10b encoder bypass 1 = Enable 8b/10b encoder bypass