Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2079
31
28
24
20
16
12
8
4
0
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
se
rv
ed
505
re
se
rv
ed
506
re
g_tx2_stagger_m
as
k_4_0
i_
cl
kb
u
f_
iclke
n_
ov
rd
i_
cl
kb
u
f_
q
clke
n_
ov
rd
re
se
rv
ed
503
i_
cl
kb
u
f_
txc
lkm
u
xe
n_
ov
rd
re
se
rv
ed
504
re
g_tx
2_c
m
m
dis
p
ar
ity
re
g_t
x1
_
ct
rl_o
ve
rrid
e
re
g_t
x2
_
ct
rl_o
ve
rrid
e
reg_tx2_txt
erm_vcc
_
1
reg_tx2_txt
erm_vcc
_
0
reg_tx
2
_
tx
de
trxl
pbk
reg_tx2_tx
electidle
re
g_tx2_tx
complian
ce
reg_tx2_tx
oneszero
es
re
g_tx2_po
w
erdown_1_0
o_
ca
p
tes
te
n
_
h
i_cap
tes
tout
fus
e_o
ve
rrid
e
i_clkbuf_ibi
ase
n
_o
vrd
re
g_lanedesk
ew_
str
ap_o
vrd____________
re
g_lane_re
vers
e_________
____________
re
g_le
ft_t
xfifo_rst
_
mast
er
___________
reg_r
ight_txfi
fo_rst_master__________
Bit
Range
Default &
Access
Description
31:30
0h
RW
reserved505:
reserved
29
0h
RW
reserved506:
reserved
28:24
Fh
RW
reg_tx2_stagger_mask_4_0:
Mask bit for lane number. Used to group lanes for
staggering. for tx2
23
0h
RW
i_clkbuf_iclken_ovrd:
I-Clock Override for the DataLane
22
0h
RW
i_clkbuf_qclken_ovrd:
Q-Clock Override for the DataLane
21
0h
RW
reserved503:
reserved
20
0h
RW
i_clkbuf_txclkmuxen_ovrd:
TX Clock Selection Mux Override
19
0h
RW
reserved504:
reserved
18
0h
RW
reg_tx2_cmmdisparity:
Sets the initial disparity during Compliance Measurement
Mode, used together with pcs_txcompliance pulse. For TX2 0 = set negative disparity 1
= set positive disparity
17
0h
RW
reg_tx1_ctrl_override:
overrides input parameter/controls for tx1
16
0h
RW
reg_tx2_ctrl_override:
overrides input parameter/controls for tx2
15
0h
RW
reg_tx2_txterm_vcc_1:
Override for txterm_vcc strap[1] for tx2 in DP family.
Override enable for inspeccmm for non-DP families (reg_inspeccmm_ovrd_enable).
14
0h
RW
reg_tx2_txterm_vcc_0:
Override for txterm_vcc strap[0] for tx2 in DP family.
Override value for inspeccmm for non-DP families (reg_inspeccmm_ovrd_value).
13
0h
RW
reg_tx2_txdetrxlpbk:
Override for i_txdetrxlpbk for tx2