Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2081
17.19.14 PCS_DWORD13 (pcs_dword13)—Offset 34h
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Description
31
0h
RW
reg_txfsm_200ns_ovrd:
Override reg_txfsm_200ns_delay+G2
30:24
0h
RW
reg_txfsm_200ns_delay_6_0:
Override value of counter for 200ns delay between
txen and txloadgenen
23
0h
RW
reg_loadgen2txen_fall_ovrd:
reserved
22:20
2h
RW
reg_tx2_stagger_mult_2_0:
Stagger multiplier for Rx (or Tx1) (Same decoding as
tx1_stagger_mult[2:0]) For Display, this multiplier applies to Tx2. For non-Display
PHYs, this multiplier applies to the Rx. The multiplier limit for the Rx is 8x (3'b100);
anything beyond that is invalid.
19
0h
RW
reg_lanestagger_by_group:
When = 1, uses group number for lane staggering, by
devalues lane number is used.
18:16
5h
RW
reg_tx1_stagger_mult_2_0:
Stagger multiplier for Tx (or Tx1) These bits set the
lane staggering multiplier for the transmitter based on the 'linkclk' period. 000 - 0x 001
- 1x 010 - 2x 011 - 4x 100 - 8x 101 - 16x 110 - 32x 111 - 64x For Display, this
multiplier applies to Tx1.
15:14
0h
RW
reserved509:
reserved
13
0h
RW
reserved510:
reserved
12:8
Fh
RW
reg_tx1_stagger_mask_4_0:
Mask bit for lane number. Used to group lanes for
staggering
7
0h
RW
reserved507:
reserved
6
0h
RW
reg_lanestagger_strap_ovrd:
When 1 config override for lane stagger strap (bits
[4:0] of this register) is selected
5
0h
RW
reserved508:
reserved
4:0
0h
RW
reg_lanestagger_strap_4_0:
Override for lane stagger strap
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword13:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
visa_en
re
se
rv
ed
512
visa_clk_s
el
1_4_0
visa_lan
e_
se
l1_7_0
visa_b
ypass
re
se
rv
ed
511
visa_clk_s
el
0_4_0
visa_lan
e_
se
l0_7_0