Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2083

Default: 04100300h

29

0h

RW

Slow Clock Override Enable When set 1'b1, reg_slowclocken 

and reg_sclk250en are valid. When cleared 1'b0, output of FSM will drive slow clock 

enable.

28:24

0h

RW

reserved

23:20

7h

RW

CML Mux strength control

19:16

Ah

RW

RX CML driver strength

15:12

0h

RW

I clk phase correction control

11:8

0h

RW

Q clk phase correction control

7

0h

RW

Iclk phase correction enable.

6

0h

RW

Qclk phase correction enabled.

5

0h

RW

Phase correction bypass.

4

1h

RW

Slow clock 1 enable Only valid if slow clock override enable is set 1'b1

3

1h

RW

Slow clock 2 enable Only valid if slow clock override enable is set 1'b1

2:0

0h

RW

Upper 3 bits of a 7-bit counter that counts number of COM 

characters found. Used for special SAPIS mode where spread spectrum clocking can be 

utilized. Note: This register is used in conjunction with another PCS register 

cri_kalignmode[1:0] = 10 Register value Minimum COM count to achieve symbol lock 

000 - 18 001 - 34 010 - 50 011 - 66 100 - 82 101 - 98 110 - 114 111 - 130

Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write