Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2086

Datasheet

Default: 01000001h

23:18

0h

RW

reserved

17:16

0h

RW

Pattern Checker Even/Odd Bit Error Mask Select 00 : no 

masking; all errors will be counted 01: select odd path, mask even path; only errors on 

bits [1,3,5,7,9] are counted 10: select even path, mask odd path; only errors on bits 

[0,2,4,6,8] are counted 11: reserved;

15:12

0h

RW

reserved

11:10

0h

RW

Local Compare Engine 2 Pattern Source In a lane with two 

Tx paths, this selects between using Pattern Buffer or PRBS as source of LCE patterns 

for the second LCE. The DFXLCEPATSRC selects for the first LCE. 0 : Pattern Buffer 

(default) 1 : PRBS

9:8

0h

RW

Local Compare Engine Pattern Source. Selects between using 

Pattern Buffer or PRBS as source of LCE patterns. 00 : Pattern Buffer; use LCE default 

training pattern; 01: Pattern Buffer; use the first 40b of pattern buffer for training. 10: 

PRBS; use LCE default training pattern; 11: PRBS; use the first 40b of pattern buffer for 

training.

7:6

0h

RW

reserved

5:4

0h

RW

TxLoadGen Pulse Width Control Controls the pulse width of 

txloadgenen from PCS to Tx upar. This is used in MAC inititated digital far end loopback 

mode in PCIE family. 00 - txloadgenen pulse width is 4 symbol clocks (default) 01- 

txloadgenen pulse width is 2 symbol clocks 10 - txloadgenen pulse not generated 11 - 

txloadgenen pulse width is 6 symbol clocks

3

0h

RW

TxHighPowerEI Override Mode Enable 0 - TxHighPowerEI 

to TxuPAR driven by Logic 1 - TxHighPowerEI to TxuPAR driven by override register 

value(s).

2

0h

RW

Tx1HighPowerEI Override Value Valid when 

cri_txhighpowerei_ovrden = 1'b1. 0 - Tx1HighPowerEI disabled 1 - Tx1HighPowerEI 

enabled

1

0h

RW

Tx2HighPowerEI Override Value Valid when 

cri_txhighpowerei_ovrden = 1'b1. 0 - Tx2HighPowerEI disabled 1 - Tx2HighPowerEI 

enabled

0

1h

RW

P2 Fast Exit Mode Enable Common Mode sustainer will be enabled 

during P2 when this bit is asserted. 1: P2 Fast Exit Mode Enable 0: P2 Fast Exit Mode 

Disable

Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write