Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2091
17.19.22 PCS_DWORD21 (pcs_dword21)—Offset 54h
Access Method
Default: 80808080h
Bit
Range
Default &
Access
Description
31:24
80h
RW
rxvgarccode_7_0:
Rx VGA Rcomp Codes These bits are the final binary code used by
the Rx VGA. This block only uses the X upper MSBs of this value. Writing to this register
will override the rcomp code to the Rx VGA. An LRC Ready pulse must be generated to
the Rx VGA target for this value to take effect. [7:n] - compensation code sent to Iref
[n-1:0] - remaining LSBs from scaling and offset calculation
23:16
80h
RW
rxtermrccode_7_0:
Rx Termination Rcomp Codes These bits are the final binary code
used by the Rx termination. This block only uses the 7 upper MSBs of this value. Writing
to this register will override the rcomp code to Rxterm. An LRC Ready pulse must be
generated to the Rxterm target for this value to take effect. [7:1] - compensation code
sent to Rxterm [0] - remaining LSB from scaling and offset calculation
15:8
80h
RW
txrccode_7_0:
Tx Rcomp Codes These bits are the final binary code used by the Tx.
This block only uses the 7 upper MSBs of this value. Writing to this register will override
the rcomp code to the Tx. An LRC Ready pulse must be generated to the Tx target for
this value to take effect. [7:1] - compensation code sent to Tx [0] - remaining LSB from
scaling and offset calculation
7:0
80h
RW
irefrccode_7_0:
Iref Rcomp Codes These bits are the final binary code used by the
Iref block. This block only uses the 6 upper MSBs of this value. Writing to this register
will override the rcomp code to the Iref block. An LRC Ready pulse must be generated
to the Iref target for this value to take effect. [7:2] - compensation code sent to Iref
[1:0] - remaining LSBs from scaling and offset calculation
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword21:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
rxvgarc
scale_7_0
rx
te
rmrc
scale_7_0
txrc
scale_7_0
ir
ef
rc
scale_7_0
Bit
Range
Default &
Access
Description
31:24
80h
RW
rxvgarcscale_7_0:
Rx VGA Rcomp Scale Multiplier The LRC code is multiplied by this
value before applying the offset to generate the final rxvgarccode. 0xFF:
Scale=1.99219 0xC0: Scale=1.5 0x80: Scale=1.0 0x40: Scale=0.5 0x00: Scale=0
23:16
80h
RW
rxtermrcscale_7_0:
Rx Termination Rcomp Scale Multiplier The LRC code is multiplied
by this value before applying the offset to generate the final rxtermrccode. 0xFF:
Scale=1.99219 0xC0: Scale=1.5 0x80: Scale=1.0 0x40: Scale=0.5 0x00: Scale=0
15:8
80h
RW
txrcscale_7_0:
Tx Rcomp Scale Multiplier The LRC code is multiplied by this value
before applying the offset to generate the final txrccode. 0xFF: Scale=1.99219 0xC0:
Scale=1.5 0x80: Scale=1.0 0x40: Scale=0.5 0x00: Scale=0
7:0
80h
RW
irefrcscale_7_0:
Iref Rcomp Scale Multiplier The LRC code is multiplied by this value
before applying the offset to generate the final irefrccode. 0xFF: Scale=1.99219 0xC0:
Scale=1.5 0x80: Scale=1.0 0x40: Scale=0.5 0x00: Scale=0