Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2093
17.19.25 PCS_DWORD24 (pcs_dword24)—Offset 60h
Access Method
Default: 0001C020h
Bit 
Range
Default & 
Access
Description
31:24
0h
RW
iclkqcfg_spare_7_0: 
(Bonus bits for Data Lane Clk Distrubtion block)
23
0h
RW
iclkicfg_spare_7: 
Repurposed for IREF backup mode in DL Select bit to enable diode 
based IREF in DL 0 - functional mode, use IREFGEN loop output 1 - bypass IREF loop, 
use diode connected PMOS output Ensure IREF loop amp is enabled by forcing 
reg_ivrefen and ivrefen_ovrd to 1
22:19
3h
RW
iclkicfg_spare_6_3: 
TX MUX tail current strength setting
18:16
0h
RW
iclkicfg_spare_2_0: 
CLK Distribution Monitor MUX Select
15:12
0h
RW
reserved526: 
reserved
11:8
8h
RW
i_drvcfg_3_0: 
CLK: Driver Tail Current Control
7:4
8h
RW
i_ploadcfg_3_0: 
CLK: Pbias Ref Current Selection
3:0
8h
RW
ipbiasctrl_3_0: 
CLK: Pmos-Load Pbias Voltage Control
Type: 
Message Bus Register
(Size: 32 bits)
pcs_dword24: 
Op Codes:
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0
res
er
ved
52
8
res
er
ved
52
7
cr
i_lanere
se
t_c
lkgatectl
cr
i_lanere
qforc
e
cri
_
su
sc
lkdis
able
_
de
la
y_4_0
cr
i_da
ta
_dync
lkgate_m
ode_1_
0
cr
i_e
ios
_w
aittime
_o
vr
en
cr
i_eios_w
aittime_6_
0
Bit 
Range
Default & 
Access
Description
31:24
0h
RW
reserved528: 
reserved
23:17
0h
RW
reserved527: 
reserved