Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2097
17.20.3
TX_DWORD2 (tx_dword2)—Offset 8h
Access Method
Default: 5580983Ah
17.20.4
TX_DWORD3 (tx_dword3)—Offset Ch
Access Method
Default: 0C782040h
7:6
0h
RO
reserved505:
reserved
5:0
0h
RW
ofrcr2short0_5_0:
number of slices in R2 for swing 0 (FS) MSB has no effect.
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 0 1 0
om
ar
gin
0
10_7_0
om
ar
gin
0
00_7_0
oun
iqtr
ansc
ale
_7_0
re
se
rv
ed
511
ofrc
slices_6_0
Bit
Range
Default &
Access
Description
31:24
55h
RW
omargin010_7_0:
factor (X/128) of slices to use in main-R1 for full swing level. Used
for ~2/3Vp2p
23:16
80h
RW
omargin000_7_0:
factor (X/128) of slices to use in main-R1 for full swing level. Used
for ~1V p2p. To be used in Gen2 mode (Gen1/Gen2 depend on dataratefit and
downscaleamp register)
15:8
98h
RW
ouniqtranscale_7_0:
scales the number of slices defined the ref circuit (or R-comp
circuit) by factor of ouniqtranscale[7:0]/128 The scaled amount of slices might be used
in the full-swing Uis according to ouniqetrangenmethod[1:0] The scaled amount of
slices might be used in the full-swing Uis according to oscaledcompmethod[1:0]
7
0h
RO
reserved511:
reserved
6:0
3Ah
RW
ofrcslices_6_0:
number of used slices if forced Used in compensated GPIO mode
Type:
Message Bus Register
(Size: 32 bits)
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write