Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2102
Datasheet
17.20.9
TX_DWORD8 (tx_dword8)—Offset 20h
Access Method
Default: 0600AA80h
21:19
7h
RW
oslrctrlr2_l_2_0: 
Slew rate trimming of driver in R2 resistor for gen1. '000' - disabled 
'001' - slowest '111' - fastest
18:16
0h
RW
oslrctrlr2_h_2_0: 
Slew rate trimming of driver in R2 resistor for gen1 '111' - disabled 
(emulates suspend mode) '110' - slowest '000' - fastest
15:14
0h
RO
reserved522: 
reserved
13:11
7h
RW
oslrctrl_l_2_0: 
Slew rate trimming of driver in R1 resistor for gen1. '000' - disabled 
'001' - slowest '111' - fastest
10:8
0h
RW
oslrctrl_h_2_0: 
Slew rate trimming of driver in R1 resistor for gen1 '111' - disabled 
(emulates suspend mode) '110' - slowest '000' - fastest
7:6
0h
RO
reserved521: 
reserved
5:0
3Fh
RW
or2bypass_5_0: 
Number of open R2s in normal EI (electrical idle) Used in DFTs with 
other values (leg connectivity scan all power of 2s) read also notes on obypbycomp. 
MSB has no effect.
Bit 
Range
Default & 
Access
Description
Type: 
Message Bus Register
(Size: 32 bits)
tx_dword8: 
Op Codes:
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0
on
tlpdtime
_7_0
of
rcdcco
up_1_0
ob
yp
by
co
mp
ob
ypdftmode
_4_0
odftpis
o
data1_7_0
odftpis
o
data0_1_0
re
se
rv
ed
529
re
se
rv
ed
528
Bit 
Range
Default & 
Access
Description
31:24
6h
RW
ontlpdtime_7_0: 
[after step 1 of pullup] time (ick_susslow cycles) to wait (step 2) 
and let the pads leak downwards before comparing pads to Vref to detemine if the pad 
exceeded Vref as a result of leakage.
23:22
0h
RW
ofrcdccoup_1_0: 
00
21
0h
RW
obypbycomp: 
0' the amount of slices used in dftbypmode is by 'nswbypass', 
'pswbypass' and 'r2bypass' registers '1' the amount of slices used is by 'slices' from 
swing-control block. Number of slices in R2 in EI - is also affected by this bit
20:16
0h
RW
obypdftmode_4_0: 
selects the DFT mode. 5'h00 - DFT_OFF 5'h01 - DFTHIZ 5'h02 - 
DFTEI 5'h03 - DFTFELB 5'h04 - DFTALL1DIF 5'h05 - DFTALL0DIF 5'h06 - DFTALL1SE 
5'h07 - DFTALL0SE 5'h08 - DFTDAC 5'h09 - DFTFRCBEAC 5'h0a - DFTOBS 5'h0c - DFT 
ASYNC MODE OFF 5'h0d - DFT ASYNC MODE Tx (output) 5'h0e - DFT ASYNC MODE Rx 
(input) 5'h0f - DFT ASYNC MODE Both (inout) 5'h10 - DFTPISOLOAD 5'h12 - 
DFTEISTRNG