Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2104
Datasheet
17.20.11 TX_DWORD10 (tx_dword10)—Offset 28h
Access Method
Default: 00000000h
15:8
Ch
RW
orcvdtctputime_7_0:
Time (ick_susslow cycles) to wait (a.k.a. step 2) before
comparing pads to Vref to detemine if there is a receiver on the far end. Value should
be by the following Table: Sus-clock rate P1269.8 P1271.x 25MHz - 27MHz 9 12 25MHz
- 62.5MHz 35 43 37.5MHz - 100MHz 64 76 62.5MHz - 125MHz 83 98
7:0
6h
RW
ontlputime_7_0:
[after step 1 of pulldown] time (ick_susslow cycles) to wait (step 2)
and let the pads leak upwards before comparing pads to Vref to detemine if the pad
exceeded Vref as a result of leakage.
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
tx_dword10:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ispare
re
ad_7
_0
re
se
rv
ed
5
3
2
re
se
rv
ed
5
3
1
ircvd
tctc
m
p
out
idftcaptests
ig
idftrc
vdetec
ted
txn
id
ftrc
vdetec
ted
txp
idft
rcvde
tectfinished
intlfinished
intl
pass
_3
_0
Bit
Range
Default &
Access
Description
31:24
X
RO
ispareread_7_0:
spare reg read
23:16
0h
RO
reserved532:
reserved
15:10
0h
RO
reserved531:
reserved
9
0h
RO
ircvdtctcmpout:
Flash Comparator Output Value
8
X
RO
idftcaptestsig:
reserved
7
0h
RO
idftrcvdetectedtxn:
Receive Detect Result for Txn
6
0h
RO
idftrcvdetectedtxp:
Receive Detect Result for Txp
5
0h
RO
idftrcvdetectfinished:
Receive Detect Process status
4
X
RO
intlfinished:
indication of NTL finished
3:0
X
RO
intlpass_3_0:
the four outputs of NTL test