Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2107
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
otx
clkbypsel_1_0
ofr
cdat
ar
atefit_2_0
odist
xfe
lbpin
otx
clkamp
b
yp
sn
ot
xc
lka
m
pb
yp
sp
re
se
rv
ed
539
od
fxanamux
en
odfxanamuxsel_1_0
obs
_
tx_gated_s
upply_1_0
re
se
rv
ed
538
oobsdigsele
ct
upn_3_0
oo
bs
digsele
ctupp_3_0
oobsdigsele
ct
do
w
n
n_3_0
oo
bs
digsele
ctdownp_3_0
Bit
Range
Default &
Access
Description
31:30
0h
RW
otxclkbypsel_1_0:
Select if to bypass the divided normal clock with some other clock.
2'b00: Don't bypass. Regular clock. 2'b01: bypass the RX clock - dataratefit must be
'11' 2'b10: Reserved 2'b11: bypass the sparetxclk clock - dataratefit must be '11'
29:27
0h
RW
ofrcdataratefit_2_0:
Forces TX data rate 3'b0XX - don't force a velue. get it from the
I/F pin 3'b100 - no divide (2UIs per clock cyc) 3'b101 - divide by 2 3'b110 - divide by 4
3'b111 - divide by 8 - used also for bypassing with other clocks
26
0h
RW
odistxfelbpin:
when asserted - disables the i_txfelben pin at the interface and force it
0. (needed in case the pin is asserted in KX or sata1 mode)
25
0h
RW
otxclkampbypsn:
0': Normal operation '1': Enable of the passgate connected from the
analog clock N to the control of the DC correction cell. The feedback OTA is disabled.
24
0h
RW
otxclkampbypsp:
0': Normal operation '1': Enable of the passgate connected from the
analog clock P to the control of the DC correction cell. The feedback OTA is disabled.
23
0h
RO
reserved539:
reserved
22
0h
RW
odfxanamuxen:
Enables analog signals probing mux out. When enabled the Vref of
Tx-detect-Rx circuit is observed. Note that only one lane is allowed to have a the analog
mux enabled to avoid collisions.
21:20
0h
RW
odfxanamuxsel_1_0:
selects analog signal to be sent to analog port in common lane.
This bus has no affect at all currently because there is only one analog signal for
observation which is observed by odfxanamuxen
19:18
0h
RW
obs_tx_gated_supply_1_0:
Monitor gated vcc supply to Tx upar
17:16
0h
RO
reserved538:
reserved
15:12
0h
RW
oobsdigselectupn_3_0:
selects data to be sent to observability port output
'o_obsup_nsg'. Same mapping as oobsdigselectdownn[3:0]
11:8
0h
RW
oobsdigselectupp_3_0:
selects data to be sent to observability port output
'o_obsup_psg'. Same mapping as oobsdigselectdownp[3:0]
7:4
0h
RW
oobsdigselectdownn_3_0:
Reserved.
3:0
0h
RW
oobsdigselectdownp_3_0:
Reserved.