Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2109
17.20.15 TX_DWORD14 (tx_dword14)—Offset 38h
Access Method
Default: 00400000h
Type:
Message Bus Register
(Size: 32 bits)
tx_dword14:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
os
par
e1_1_0
osimmode
ontlmod
ep
in2p
in
ofrc
datapathdi
s
ofrc
datapathen
of
rcd
rvb
ypdi
s
of
rcd
rvb
ypen
odftt
xclkc
apte
ste
n
ot
xd
ccb
yp
s_l
of
rcn
m
os
32idv_2_0
of
rcpm
os
32idv_2_0
visa_en
ov
isa1_clks
el_2_0
ov
isa1_lan
es
el
_3_0
ov
is
a_
by
p
ass
ov
isa0_clks
el_2_0
ov
isa0_lan
es
el
_3_0
Bit
Range
Default &
Access
Description
31:30
0h
RW
ospare1_1_0:
reserved
29
0h
RW
osimmode:
Counter threshold of receive-detect, NTL, strong-common-mode is
shortened dramatically for fast simulation porpuses. (does not impose risk to circuitly
but electrical spec will not met)
28
0h
RW
ontlmodepin2pin:
0 - NTL procedure will be done per pad while both pads are pulled
to the same rail. 1 - NTL procedure will be done per pad while the pads are pulled to
opposite rails.
27
0h
RW
ofrcdatapathdis:
DFT feature to optionaly be used with other registers
26
0h
RW
ofrcdatapathen:
DFT feature to optionaly be used with other registers
25
0h
RW
ofrcdrvbypdis:
DFT feature to optionaly be used with other registers
24
0h
RW
ofrcdrvbypen:
DFT feature to optionaly be used with other registers
23
0h
RW
odfttxclkcaptesten:
Enables the finger capacitor quality check in the DCC block in Tx-
clock block. The test is for shorts between the capacitor terminals.
22
1h
RW
otxdccbyps_l:
Tx DCC Bypass Override Puts DCC (duty cycle correction) circuit in
bypass mode 0 - clock's duty cycle is not fixed
21:19
0h
RW
ofrcnmos32idv_2_0:
change the value iabut_idvpmos32_h[1:0] pushes to txclk
3'b0?? - don't affect the idv comp 3'b100 - pull the idv information to be always at slow
3'b101 - pull the idv information a bit slower. 3'b110 - pull the idv information a bit
faster. 3'b111 - pull the idv information to be always at fast
18:16
0h
RW
ofrcpmos32idv_2_0:
change the value iabut_idvpmos32_h[1:0] pushes to txclk
3'b0?? - don't affect the idv comp 3'b100 - pull the idv information to be always at slow
3'b101 - pull the idv information a bit slower. 3'b110 - pull the idv information a bit
faster. 3'b111 - pull the idv information to be always at fast
15
0h
RW
visa_en:
VISA Enable for the Tx VISA logic
14:12
0h
RW
ovisa1_clksel_2_0:
VISA Clock Select for Lane1. Selects the source synchronous
clock to be used for data being sent on lane1.