Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
USB Host Controller Interfaces (xHCI, EHCI)
Intel
®
Atom™ Processor E3800 Product Family
2114
Datasheet
Note: xHCI (3.0) SS is the debug port for xHCI controller.
Note: EHCI (1/2.0) Port 1 is the debug port of the EHCI controller
Note: EHCI (1/2.0) Port 1 is the debug port of the EHCI controller
18.2
USB 3.0 xHCI (Extensible Host Controller
Interface)
The xHCI compliant host controller can control up to 7 USB host ports. It supports
devices conforming to USB 1.x to 3.0 at bit rates up to 5 Gbps.
devices conforming to USB 1.x to 3.0 at bit rates up to 5 Gbps.
18.2.1
Features of USB 3.0 Host
The USB 3.0 Super Speed data interface is a four wire differential (TX and RX pairs)
interface that supports simultaneous bi-directional data transmission. The interface
supports a bit rate of 5 Gbps with a maximum theoretical data throughput over 3.2
Gbps due to 8b/10b symbol encoding scheme and protocol overhead (link flow control,
packet framing and protocol overhead).
interface that supports simultaneous bi-directional data transmission. The interface
supports a bit rate of 5 Gbps with a maximum theoretical data throughput over 3.2
Gbps due to 8b/10b symbol encoding scheme and protocol overhead (link flow control,
packet framing and protocol overhead).
Low Frequency Periodic signaling (LFPS) is used to communicate initialization, training
and power management information across a link that is in low power link state without
using Super Speed signaling. This reduces power consumption.
and power management information across a link that is in low power link state without
using Super Speed signaling. This reduces power consumption.
The USB3.0 port may be paired with any USB2 port at the connector – selection of any
USB2 port other than port 0 will require the appropriate mapping.
USB2 port other than port 0 will require the appropriate mapping.
shows the
USB3 port paired with USB2 port 0.
USB3.0 Controller Features
•
Supported by xHCI software host controller interface
•
USB3 port disable
•
Supports local dynamic clock gating and trunk clock gating
•
Supports USB 3.0 LPM (U0, U1, U2, and U3) and also a SS Disabled low power
state
state
Figure 105.xHCI and EHCI Port Mapping
0
1
0
1
0
1
0
1
EHCI
xHCI
(1/2.0)
Port 3
(1/2.0)
Port 2
(1/2.0)
Port 1
(1/2.0)
Port 0
(3.0)
SS
(2.0)
HSIC 0
(2.0)
HSIC 1
PCI xHCI
USB2HCSEL
[3]
[2]
[1]
[0]
USB 1/2/3
Connector
P1-4 SSP1
P5
P6
P4
P3
P2
P1