Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2123
18.6.4
Device Status (STS)—Offset 6h
Access Method
Default: 0290h
6
0b
RW
Parity Error Response (PER):
When set to 1, the XHCI Host Controller will check for
correct parity (on its internal interface) and halt operation when bad parity is detected
during the data phase as recommended by the XHCI specification. Note that this applies
to both requests and completions from the system interface. This bit must be set in
order for the parity errors to generate SERR#.
Power Well:
Core
5
0b
RO
VGA Palette Snoop (VPS):
Reserved.
Power Well:
Core
4
0b
RO
Memory Write Invalidate (MWI):
Reserved.
Power Well:
Core
3
0b
RO
Special Cycle Enable (SCE):
Reserved.
Power Well:
Core
2
0b
RW
Bus Master Enable (BME):
When set, it allows XHC to act as a bus master. When
cleared, it disable XHC from initiating transactions on the system bus.
Power Well:
Core
1
0b
RW
Memory Space Enable (MSE):
This bit controls access to the XHC Memory Space
registers. If this bit is set, accesses to the XHC registers are enabled. The Base Address
register for the XHC should be programmed before this bit is set.
Power Well:
Core
0
0b
RO
I/O Space Enable (IOSE):
Reserved as 0. Read-Only.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 16 bits)
Offset:
15
12
8
4
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
DPE
SSE
RMA
RT
A
ST
A
DE
VT
MDPED
FBBC
UDF
MC
CL
IS
RS
VD
Bit
Range
Default &
Access
Field Name (ID): Description
15
0b
RW/1C
Detected Parity Error (DPE):
This bit is set by the Intel PCH whenever a parity error
is seen on the internal interface to the XHC host controller, regardless of the setting of
bit 6 or bit 8 in the Command register or any other conditions. Software clears this bit
by writing a 1 to this bit location.
Power Well:
Core